liu.seSearch for publications in DiVA
Change search
Link to record
Permanent link

Direct link
Wu, Zhenzhi
Publications (1 of 1) Show all publications
Wu, Z. & Liu, D. (2015). High-Throughput Trellis Processor for Multistandard FEC Decoding. IEEE Transactions on Very Large Scale Integration (vlsi) Systems, 23(12), 2757-2767
Open this publication in new window or tab >>High-Throughput Trellis Processor for Multistandard FEC Decoding
2015 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 23, no 12, p. 2757-2767Article in journal (Refereed) Published
Abstract [en]

Trellis codes, including Low-Density Parity-Check (LDPC), turbo, and convolutional code (CC), are widely adopted in advanced wireless standards to offer high-throughput forward error correction (FEC). Designing a multistandard FEC decoder is of great challenge. In this paper, a trellis application specified instruction-set processor (TASIP) is presented for multistandard trellis decoding. A unified forward-backward recursion kernel with an eight-state parallel trellis structure is proposed. Based on the kernel, a datapath for multialgorithm and a shared memory subsystem are introduced. The flexibility and the compatibility are guaranteed by a programmable decoding flow and the trellis decoding instruction set. Synthesis results show that the area consumption is 2.12 mm(2) (65 nm). TASIP provides trimode FEC decoding ability with the throughput of 533, 186, and 225 Mb/s for LDPC, turbo, and 64 states CC under the clock frequency of 200 MHz, which outperforms other trimode proposals both in area efficiency and recursion efficiency. TASIP provides high-throughput decoding for current standards, including 3rd Generation Partnership Project-Long Term Evolution, 802.16e, and 802.11n, with unified architecture and high compatibility.

Place, publisher, year, edition, pages
Application-specific instruction-set processor (ASIP); forward-backward recursion (FBR); multistandard forward error correction (FEC); single instruction multiple data (SIMD); trellis decoding
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
urn:nbn:se:liu:diva-123513 (URN)10.1109/TVLSI.2014.2382108 (DOI)000365206300001 ()

Funding Agencies|National High-Tech Research and Development Program (863 Program) of China [2014AA01A705]

Available from: 2015-12-22 Created: 2015-12-21 Last updated: 2017-12-01Bibliographically approved

Search in DiVA

Show all publications