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Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures
National Chiao Tung University, Taiwan.
Novatek Corp, Taiwan.
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
National Chiao Tung University, Taiwan.
2014 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 10, 2869-2877 p.Article in journal (Refereed) Published
Abstract [en]

This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2014. Vol. 61, no 10, 2869-2877 p.
Keyword [en]
Bit-reversal circuit; fast Fourier transform (FFT); MDC; MDF; natural-order FFT output
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-112046DOI: 10.1109/TCSI.2014.2327271ISI: 000343003100011OAI: oai:DiVA.org:liu-112046DiVA: diva2:763891
Note

Funding Agencies|National Science Council, Taiwan [NSC 102-2220-E-009-009]

Available from: 2014-11-17 Created: 2014-11-13 Last updated: 2017-12-05

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Garrido Gálvez, Mario

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