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An Integrated System-on-Chip Test Framework
Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
2008 (engelsk)Inngår i: Design, Automation, and Test in Europe: The Most Influential Papers of 10 Years DATE, Dordrecht, The Netherlands: Springer , 2008, 1, s. 439-454Kapittel i bok, del av antologi (Annet vitenskapelig)
Abstract [en]

In this paper we propose a framework for the testing of system-on-chip (SOC), which includes a set of design algorithms to deal with test scheduling, test access mechanism design, test sets selection, test parallelization, and test resource placement. The approach minimizes the test application time and the cost of the test access mechanism while considering constraints on tests, power consumption and test resources. The main feature of our approach is that it provides an integrated design environment to treat several different tasks at the same time, which were traditionally dealt with as separate problems. Experimental results shows the efficiency and the usefulness of the proposed technique.

sted, utgiver, år, opplag, sider
Dordrecht, The Netherlands: Springer , 2008, 1. s. 439-454
Emneord [en]
testing, system-on-chip, SOC, framework, integrated testing
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-39641Lokal ID: 50433ISBN: 978-1-4020-6487-6 (tryckt)ISBN: 978-1-4020-6488-3 (tryckt)OAI: oai:DiVA.org:liu-39641DiVA, id: diva2:260490
Tilgjengelig fra: 2009-10-10 Laget: 2009-10-10 Sist oppdatert: 2018-01-13bibliografisk kontrollert

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