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High performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.ORCID-id: 0000-0002-0111-2384
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
2008 (engelsk)Inngår i: IET Computers and digital techniques, ISSN 1751-8601, Vol. 2, s. 305-313Artikkel i tidsskrift (Fagfellevurdert) Published
Abstract [en]

There is increasing interest about floating-point arithmetics in field programmable gate arrays (FPGAs) because of the increase in their size and performance. FPGAs are generally good at bit manipulations and fixed-point arithmetics, but they have a harder time coping with floating-point arithmetics. An architecture used to construct high-performance floating-point components in a Virtex-4 FPGA is described in detail. Floating-point adder/subtracter and multiplier units have been constructed. The adder/subtracter can operate at a frequency of 377 MHz in a Virtex-4SX35 (speed grade -12).

sted, utgiver, år, opplag, sider
2008. Vol. 2, s. 305-313
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-16563DOI: 10.1049/iet-cdt:20070075OAI: oai:DiVA.org:liu-16563DiVA, id: diva2:158401
Tilgjengelig fra: 2009-02-02 Laget: 2009-02-02 Sist oppdatert: 2015-02-18bibliografisk kontrollert
Inngår i avhandling
1. Performance driven FPGA design with an ASIC perspective
Åpne denne publikasjonen i ny fane eller vindu >>Performance driven FPGA design with an ASIC perspective
2009 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
Abstract [en]

FPGA devices are an important component in many modern devices. This means that it is important that VLSI designers have a thorough knowledge of how to optimize designs for FPGAs. While the design flows for ASICs and FPGAs are similar, there are many differences as well due to the limitations inherent in FPGA devices. To be able to use an FPGA efficiently it is important to be aware of both the strengths and oweaknesses of FPGAs. If an FPGA design should be ported to an ASIC at a later stage it is also important to take this into account early in the design cycle so that the ASIC port will be efficient.

This thesis investigates how to optimize a design for an FPGA through a number of case studies of important SoC components. One of these case studies discusses high speed processors and the tradeoffs that are necessary when constructing very high speed processors in FPGAs. The processor has a maximum clock frequency of 357~MHz in a Xilinx Virtex-4 devices of the fastest speedgrade, which is significantly higher than Xilinx' own processor in the same FPGA.

Another case study investigates floating point datapaths and describes how a floating point adder and multiplier can be efficiently implemented in an FPGA.

The final case study investigates Network-on-Chip architectures and how these can be optimized for FPGAs. The main focus is on packet switched architectures, but a circuit switched architecture optimized for FPGAs is also investigated.

All of these case studies also contain information about potential pitfalls when porting designs optimized for an FPGA to an ASIC. The focus in this case is on systems where initial low volume production will be using FPGAs while still keeping the option open to port the design to an ASIC if the demand is high. This information will also be useful for designers who want to create IP cores that can be efficiently mapped to both FPGAs and ASICs.

Finally, a framework is also presented which allows for the creation of custom backend tools for the Xilinx design flow. The framework is already useful for some tasks, but the main reason for including it is to inspire researchers and developers to use this powerful ability in their own design tools.

sted, utgiver, år, opplag, sider
Linköping: Linköping University Electronic Press, 2009. s. 165
Serie
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1237
Emneord
FPGA Optimizations, ASIC and FPGA codesign
HSV kategori
Identifikatorer
urn:nbn:se:liu:diva-16372 (URN)978-91-7393-702-3 (ISBN)
Disputas
2009-02-27, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15 (engelsk)
Opponent
Veileder
Tilgjengelig fra: 2009-02-02 Laget: 2009-01-19 Sist oppdatert: 2018-01-13bibliografisk kontrollert

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