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A Low Clock Load Conditional Flip-Flop
Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.ORCID-id: 0000-0001-8922-2360
2004 (engelsk)Inngår i: Proceedings of IEEE International System-on-Chip Conference, Santa Clara, California, USA, September 2004, 2004, s. 169-170Konferansepaper, Publicerat paper (Annet vitenskapelig)
Abstract [en]

We describe a low clock load conditional transmission-gate flip-flop aimed at reducing on-chip clock power consumption. It utilizes a scalable and simple leakage compensation technique, which injects additional leakage current in opposite direction, thus compensating for the worst-case leakage. During any low frequency operation, the flip-flop is configured as a static flip-flop with increased functional robustness. Post-layout simulations show a 30 % clock power reduction compared to a conventional static flip-flop.

sted, utgiver, år, opplag, sider
2004. s. 169-170
Emneord [en]
integrated circuit, low power, flip-flop, clock load
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-14065DOI: 10.1109/SOCC.2004.1362394OAI: oai:DiVA.org:liu-14065DiVA, id: diva2:22558
Tilgjengelig fra: 2006-10-09 Laget: 2006-10-09 Sist oppdatert: 2019-09-05
Inngår i avhandling
1. Low-Power Multi-GHz Circuit Techniques for On-chip Clocking
Åpne denne publikasjonen i ny fane eller vindu >>Low-Power Multi-GHz Circuit Techniques for On-chip Clocking
2006 (engelsk)Licentiatavhandling, med artikler (Annet vitenskapelig)
Abstract [en]

The impressive evolution of modern high-performance microprocessors have resulted in chips with over one billion transistors as well as multi-GHz clock frequencies. As the silicon integrated circuit industry moves further into the nanometer regime, three of the main challenges to overcome in order for continuing CMOS technology scaling are; growing standby power dissipation, increasing variations in process parameters, and increasing power dissipation due to growing clock load and circuit complexity. This thesis addresses all three of these future scaling challenges with the overall focus on reducing the total clock-power for low-power, multi-GHz VLSI circuits.

Power-dissipation related to the clock generation and distribution is identified as the dominating contributor of the total active power dissipation. This makes novel power reduction techniques crucial in future VLSI design. This thesis describes a new energy-recovering clocking technique aimed at reducing the total chip clock-power. The proposed technique consumes 2.3x lower clock-power compared to conventional clocking at a clock frequency of 1.56 GHz.

Apart from increasing power dissipation due to leakage also the robustness constraints for circuits are impacted by the increasing leakage. To improve the leakage robustness for sub-90 nm low clock load dynamic flip-flops a novel keeper technique is proposed. The proposed keeper utilizes a scalable and simple leakage compensation technique. During any low frequency operation, the flip-flop is configured as a static flip-flop with increased functional robustness.

In order to compensate the impact of the increasingly large process variations on latches and flip-flops, a reconfigurable keeper technique is presented in this thesis. In contrast to the traditional design for worst-case process corners, a variable keeper circuit is utilized. The proposed reconfigurable keeper preserves the robustness of storage nodes across the process corners without degrading the overall chip performance.

sted, utgiver, år, opplag, sider
Institutionen för systemteknik, 2006. s. 112
Serie
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1240
Emneord
CMOS, low-power, high-performance, flip-flop, clocking, leakage-compensation, process-variation
HSV kategori
Identifikatorer
urn:nbn:se:liu:diva-7545 (URN)91-85497-39-8 (ISBN)
Presentation
2006-03-28, Glashuset, B-huset, Campus Valla, Linköpings universitet, Linköping, 13:15 (engelsk)
Opponent
Veileder
Merknad

Report code: LiU-TEK-LIC-2006:21.

Tilgjengelig fra: 2006-10-09 Laget: 2006-10-09 Sist oppdatert: 2020-04-01

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Hansson, MartinAlvandpour, Atila

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Totalt: 169 treff
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