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Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems
Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
2003 (engelsk)Inngår i: IEE journal on computers and digital techniques / Institution of electrical engineers, ISSN 0140-1335, Vol. 150, nr 5, s. 303-312Artikkel i tidsskrift (Fagfellevurdert) Published
Abstract [en]

We present an approach to schedulability analysis for the synthesis of multicluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. We have also proposed a buffer size and worst-case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for the priority assignment and synthesis of bus access parameters aimed at producing a schedulable system with minimal buffer needs have been proposed. Extensive experiments and a real-life example show the efficiency of our approaches.

sted, utgiver, år, opplag, sider
2003. Vol. 150, nr 5, s. 303-312
Emneord [en]
schedulability analysis, multi-cluster distributed embedded systems, time-triggered, event-triggered, routing inter-cluster traffic, bus access optimization
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Identifikatorer
URN: urn:nbn:se:liu:diva-23346Lokal ID: 2781OAI: oai:DiVA.org:liu-23346DiVA, id: diva2:243660
Tilgjengelig fra: 2009-10-07 Laget: 2009-10-07 Sist oppdatert: 2018-01-13

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http://www.ida.liu.se/labs/eslab/publications/pap/db/cdt03.pdf

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