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ADC on-Chip Dynamic Test by PWM Technique
Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
2008 (engelsk)Inngår i: International Conference on Signals and Electronic Systems, IEEE , 2008, s. 15-18Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

This paper investigates the feasibility of pulse width modulation technique (PWM) for dynamic test of ADCs used for high speed applications. The requirements and limitations of digital PWM signal to noise ratio (SNR) are discussed in terms of pulse-width resolution corresponding to the choice of the carrier- and clock frequency of a pulse-width generator. The PWM SNR response is measured by FFT using coherent sampling for different PWM resolution. Low-pas filtering removing high frequency PWM components is introduced as well to improve PWM SNR and prevent intermodulation effects, which tend to hamper the harmonic distortion test (HD). As an example a 4-bit first-order SigmaDelta ADC under dynamic test is simulated and the requirements for PWM resolution with respect to SNR and HD measurements are identified.

sted, utgiver, år, opplag, sider
IEEE , 2008. s. 15-18
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-43029DOI: 10.1109/ICSES.2008.4673345Lokal ID: 70959ISBN: 78-83-88309-47-2 (tryckt)OAI: oai:DiVA.org:liu-43029DiVA, id: diva2:263886
Konferanse
International Conference on Signals and Electronic Systems, ICSES '08, 14-17 Sept, Krakow, Poland
Tilgjengelig fra: 2009-10-10 Laget: 2009-10-10 Sist oppdatert: 2010-11-17bibliografisk kontrollert
Inngår i avhandling
1. Stimuli Generation Techniques for On-Chip Mixed-Signal Test
Åpne denne publikasjonen i ny fane eller vindu >>Stimuli Generation Techniques for On-Chip Mixed-Signal Test
2010 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
Abstract [en]

With increased complexity of the contemporary very large integrated circuits the need for onchip test addressing not only the digital but also analog and mixed-signal RF blocks has emerged. The standard production test has become more costly and the instrumentation is pushed to its limits by the leading edge integrated circuit technologies. Also the chip performance for high frequency operation and the area overhead appear a hindrance in terms of the test access points needed for the instrumentation-based test. To overcome these problems, test implemented on a chip can be used by sharing the available resources such as digital signal processing (DSP) and A/D, D/A converters to constitute a built-in-self-test. In this case, the DSP can serve both as a stimuli generator and response analyzer.

Arbitrary test signals can be achieved using DSP. Specifically, the ΣΔ modulation technique implemented in software is useful to encode a single- or two-tone stimulus as a onebit sequence to generate a spectrally pure signal with a high dynamic range. The sequence can be stored in a cyclic memory on a chip and applied to the circuit under test using a buffer and a simple reconstruction filter. In this way ADC dynamic test for harmonic and intermodulation distortion is carried out in a simple setup. The FFT artifacts are avoided by careful frequency planning for low-pass and band-pass ΣΔ encoding technique. A noise shaping based on a combination of low- and band-pass ΣΔ modulation is also useful providing a high dynamic range for measurements at high frequencies that is a new approach. However, a possible asymmetry between rise and fall time due to CMOS process variations in the driving buffer results in nonlinear distortion and increased noise at low frequencies. A simple iterative predistortion technique is used to reduce the low frequency distortion components by making use of an on-chip DC calibrated ADC that is another contribution of the author.

Some tests, however, like the two-tone RF test that targets linearity performance of a radio receiver, require test stimuli based on a dedicated hardware. For the measurement of the thirdor second-intercept point (IP3/IP2) a spectrally clean stimulus is essential. Specifically, the second- or third-order harmonic or intermodulation products of the stimulus generator should be avoided as they can obscure the test measurement. A challenge in this design is the phase noise performance and spurious tones of the oscillators, and also the distortion-free addition of the two tones. The mutual pulling effect can be minimized by layout isolation techniques.

A new two-tone RF generator based on a specialized phase-locked loop (PLL) architecture is presented as a viable solution for IP3/IP2 on-chip test. The PLL provides control over the frequency spacing of two voltage controlled oscillators. For the two-tone stimulus a highly linear analog  adder is designed to limit distortion which could obscure the IP3 test. A specialized feedback circuit in the PLL is proposed to overcome interference by the reference spurs. The circuit is designed using 65 nm CMOS process. By using a fine spectral resolution the observed noise floor can be reduced to enable the measurement of second- or third-order intermodulation product tones. This also reflects a tradeoff between the test time and the test performance. While the test time to collect the required number of samples can be of milliseconds the number of samples need not be excessive, since the measurements are carried out at the receiver baseband, where the required sampling frequency is relatively low.

sted, utgiver, år, opplag, sider
Linköping: Linköping University Electronic Press, 2010. s. 162
Serie
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1350
HSV kategori
Identifikatorer
urn:nbn:se:liu:diva-61712 (URN)978-91-7393-288-2 (ISBN)
Disputas
2010-12-02, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15
Opponent
Veileder
Tilgjengelig fra: 2010-11-17 Laget: 2010-11-17 Sist oppdatert: 2010-11-17bibliografisk kontrollert

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