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High Bandwidth, Low-Latency Global Interconnect
Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
2003 (Engelska)Ingår i: VLSI Circuits and Systems, Proceedings of the SPIE, Vol. 5117, Gran Canaria, Spain, May, 2003, s. 126-134Konferensbidrag, Publicerat paper (Övrigt vetenskapligt)
Abstract [en]

Global interconnects have been identified as a serious limitation to chip scaling, due to their limited bandwidth and large delay. A critical analysis of intrinsic limitations of electrical interconnect indicates that these limitations can be overcome. This basic analysis is presented, together with design constraints. We demonstrate a scheme for this, based on the utilization of upper-level metals as transmission lines. A global communication architecture based on a global mesochronous, local synchronous approach allows very high data-rate per wire and therefore very high bandwidth in buses of limited width. As an example, we demonstrate a 320µm wide bus with a capacity of 160Gb/s in a nearly standard 0.18µm process.

Ort, förlag, år, upplaga, sidor
2003. s. 126-134
Nyckelord [en]
interconnect, low latency, high bandwidth, global
Nationell ämneskategori
Teknik och teknologier
Identifikatorer
URN: urn:nbn:se:liu:diva-13907DOI: 10.1117/12.499957OAI: oai:DiVA.org:liu-13907DiVA, id: diva2:22179
Tillgänglig från: 2006-07-18 Skapad: 2006-07-18 Senast uppdaterad: 2009-06-05
Ingår i avhandling
1. Efficient high-speed on-chip global interconnects
Öppna denna publikation i ny flik eller fönster >>Efficient high-speed on-chip global interconnects
2006 (Engelska)Doktorsavhandling, sammanläggning (Övrigt vetenskapligt)
Abstract [en]

The continuous miniaturization of integrated circuits has opened the path towards System-on-Chip realizations. Process shrinking into the nanometer regime improves transistor performancewhile the delay of global interconnects, connecting circuit blocks separated by a long distance, significantly increases. In fact, global interconnects extending across a full chip can have a delay corresponding to multiple clock cycles. At the same time, global clock skew constraints, not only between blocks but also along the pipelined interconnects, become even tighter. On-chip interconnects have always been considered RC-like, that is exhibiting long RC-delays. This has motivated large efforts on alternatives such as on-chip optical interconnects, which have not yet been demonstrated, or complex schemes utilizing on-chip F-transmission or pulsed current-mode signaling.

In this thesis, we show that well-designed electrical global interconnects, behaving as transmission lines, have the capacity of very high data rates (higher than can be delivered by the actual process) and support near velocity-of-light delay for single-ended voltage-mode signaling, thus mitigating the RC-problem. We critically explore key interconnect performance measures such as data delay, maximum data rate, crosstalk, edge rates and power dissipation. To experimentally demonstrate the feasibility and superior properties of on-chip transmission line interconnects, we have designed and fabricated a test chip carrying a 5 mm long global communication link. Measurements show that we can achieve 3 Gb/s/wire over the 5 mm long, repeaterless on-chip bus implemented in a standard 0.18 μm CMOS process, achieving a signal velocity of 1/3 of the velocity of light in vacuum.

To manage the problems due to global wire delays, we describe and implement a Synchronous Latency Insensitive Design (SLID) scheme, based on source-synchronous data transfer between blocks and data re-timing at the receiving block. The SLIDtechnique not onlymitigates unknown globalwire delays, but also removes the need for controlling global clock skew. The high-performance and high robustness capability of the SLID-method is practically demonstrated through a successful implementation of a SLID-based, 5.4 mm long, on-chip global bus, supporting 3 Gb/s/wire and dynamically accepting ± 2 clock cycles of data-clock skew, in a standard 0.18 μm CMOS porcess.

In the context of technology scaling, there is a tendency for interconnects to dominate chip power dissipation due to their large total capacitance. In this thesis we address the problem of interconnect power dissipation by proposing and analyzing a transition-energy cost model aimed for efficient power estimation of performancecritical buses. The model, which includes properties that closely capture effects present in high-performance VLSI buses, can be used to more accurately determine the energy benefits of e.g. transition coding of bus topologies. We further show a power optimization scheme based on appropriate choice of reduced voltage swing of the interconnect and scaling of receiver amplifier. Finally, the power saving impact of swing reduction in combination with a sense-amplifying flip-flop receiver is shown on a microprocessor cache bus architecture used in industry.

Ort, förlag, år, upplaga, sidor
Institutionen för systemteknik, 2006
Serie
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 992
Nyckelord
Microelectronics, Global Interconnects, On-Chip Interconnects, Velocity-of-Light Delay, On-Chip Communication, Low-Latency, Transmission Lines
Nationell ämneskategori
Annan elektroteknik och elektronik
Identifikatorer
urn:nbn:se:liu:diva-7123 (URN)91-85457-87-6 (ISBN)
Disputation
2006-01-27, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15 (Engelska)
Opponent
Handledare
Tillgänglig från: 2006-07-18 Skapad: 2006-07-18

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Svensson, ChristerCaputa, Peter

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