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Design and analysis of an oversampling D/A converter in DMT-ADSL systems
Royal Inst Technol, Elect Syst Design Lab, S-16440 Kista, Sweden Ericsson Microelect AB, SE-58117 Linkoping, Sweden.
Royal Inst Technol, Elect Syst Design Lab, S-16440 Kista, Sweden Ericsson Microelect AB, SE-58117 Linkoping, Sweden.
2002 (Engelska)Ingår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 32, nr 3, s. 201-210Artikel i tidskrift (Refereegranskat) Published
Abstract [en]

Oversampling sigma-delta digital-to-analog converters are crucial building blocks for telecommunication applications. To reduce power consumption, lower oversampling ratios are preferred thus high-order digital sigma-delta modulators are needed to meet the dynamic performance requirements. This paper presents an oversampling DAC with 1.104 MHz signal bandwidth for DMT-ADSL application and focuses on the design issues of the high-order one-bit multiple feedback modulators (such as the stability problem, good inband SNDR performance, limit cycles, etc.). A new approach to obtain and optimize the stable feedback coefficients has been presented. From our analysis results it is found that the extra feedback coefficients and scaling coefficients in the modulator have non-negligible impact on the behavior of the limit cycles, and design guide for selecting the scaling coefficients is provided. Finally a 5th-order modulator with an oversampling ratio of 32 and 14-bit input has been implemented in a 0.6 mum 3.3 V CMOS process and integrated into the whole DAC chip.

Ort, förlag, år, upplaga, sidor
2002. Vol. 32, nr 3, s. 201-210
Nyckelord [en]
high-order modulators, root locus analysis, NTF zeros optimization, limit cycles, sigma-delta DACs
Nationell ämneskategori
Naturvetenskap
Identifikatorer
URN: urn:nbn:se:liu:diva-48777OAI: oai:DiVA.org:liu-48777DiVA, id: diva2:269673
Tillgänglig från: 2009-10-11 Skapad: 2009-10-11 Senast uppdaterad: 2017-12-12

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