liu.seSök publikationer i DiVA
Ändra sökning
RefereraExporteraLänk till posten
Permanent länk

Direktlänk
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Annat format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annat språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf
An asynchronous architecture for modeling intersegmental neural communication
IEEE, Georgia Institute of Technology, Atlanta, GA 30332, United States, Alereon, Austin, TX.
IEEE, Georgia Institute of Technology, Atlanta, GA 30332, United States.
IEEE, Georgia Institute of Technology, Atlanta, GA 30332, United States, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, University of Linkoping, Linkoping, Sweden, NASA's Jet Propulsion Laboratory, IBM Almaden Research Center, Intel, Tau Beta Pi, Eta Kappa Nu.
IEEE, Georgia Institute of Technology, Atlanta, GA 30332, United States, Wallace H. Coulter Department of Biomedical Engineering, School of Electrical and Computer Engineering, Georgia Institute of Technology, Emory University, School of Medicine, Atlanta, GA.
2006 (Engelska)Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 14, nr 2, s. 97-111Artikel i tidskrift (Refereegranskat) Published
Abstract [en]

This paper presents an asynchronous VLSI architecture for modeling the oscillatory patterns seen in segmented biological systems. The architecture emulates the intersegmental synaptic connectivity observed in these biological systems. The communications network uses address-event representation (AER), a common neuromorphic protocol for data transmission. The asynchronous circuits are synthesized using communicating hardware processes (CHP) procedures. The architecture is scalable, supports multichip communication, and operates independent of the type of silicon neuron (spiking or burst envelopes). A 16-segment prototype system was developed, tested, and implemented, data from this system are presented. © 2006 IEEE.

Ort, förlag, år, upplaga, sidor
2006. Vol. 14, nr 2, s. 97-111
Nyckelord [en]
Address event representation (AER), Asynchronous circuits, Central pattern generator (CPG), Neurobiological modeling, Neuromorphic engineering, Silicon neuron, VLSI architecture
Nationell ämneskategori
Naturvetenskap
Identifikatorer
URN: urn:nbn:se:liu:diva-50304DOI: 10.1109/TVLSI.2005.863762OAI: oai:DiVA.org:liu-50304DiVA, id: diva2:271200
Tillgänglig från: 2009-10-11 Skapad: 2009-10-11 Senast uppdaterad: 2017-12-12

Open Access i DiVA

Fulltext saknas i DiVA

Övriga länkar

Förlagets fulltext
I samma tidskrift
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
Naturvetenskap

Sök vidare utanför DiVA

GoogleGoogle Scholar

doi
urn-nbn

Altmetricpoäng

doi
urn-nbn
Totalt: 57 träffar
RefereraExporteraLänk till posten
Permanent länk

Direktlänk
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Annat format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annat språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf