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Time-Mode Analog-to-Digital Conversion Using Standard Cells
Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
2014 (Engelska)Ingår i: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, nr 12, s. 3348-3357Artikel i tidskrift (Refereegranskat) Published
Abstract [en]

Synthesizable all-digital ADCs that can be designed, verified and taped out using a digital design flow are of interest due to a consequent reduction in design cost and an improved technology portability. As a step towards high performance synthesizable ADCs built using generic and low accuracy components, an ADC designed exclusively with standard digital cell library components is presented. The proposed design is a time-mode circuit employing a VCO based multi-bit quantizer. The ADC has first order noise-shaping due to inherent error feedback of the oscillator and sinc anti-aliasing filtering due to continuous-time sampling. The proposed architecture employs a Gray-counter based quantizer design, which mitigates the problem of partial sampling of digital data in multi-bit VCO-based quantizers. Furthermore, digital correction employing polynomial-fit estimation is proposed to correct for VCO non-linearity. The design occupies 0.026 mm when fabricated in a 65 nm CMOS process and delivers an ENOB of 8.1 bits over a signal bandwidth of 25.6 MHz, while sampling at 205 MHz. The performance is comparable to that of recently reported custom designed single-ended open-loop VCO-based ADCs, while being designed exclusively with standard cells, and consuming relatively low average power of 3.3 mW achieving an FoM of 235 fJ/step.

Ort, förlag, år, upplaga, sidor
Institute of Electrical and Electronics Engineers (IEEE), 2014. Vol. 61, nr 12, s. 3348-3357
Nyckelord [en]
ADC; all-digital; analog-to-digital; Gray-counter; linearization; polynomial-fit; standard cell; synthesizable; time-domain; time-mode; VCO-based ADC
Nationell ämneskategori
Elektroteknik och elektronik
Identifikatorer
URN: urn:nbn:se:liu:diva-113048DOI: 10.1109/TCSI.2014.2340551ISI: 000345581200004OAI: oai:DiVA.org:liu-113048DiVA, id: diva2:778352
Tillgänglig från: 2015-01-09 Skapad: 2015-01-08 Senast uppdaterad: 2017-12-05
Ingår i avhandling
1. Design of VCO-based ADCs
Öppna denna publikation i ny flik eller fönster >>Design of VCO-based ADCs
2016 (Engelska)Doktorsavhandling, sammanläggning (Övrigt vetenskapligt)
Abstract [en]

Today's complex electronic systems with billions of transistors on a single die are enabled by the aggressive scaling down of the device feature size at an exponential rate as predicted by the Moore's law. Digital circuits benefit from technology scaling to become faster, more energy efficient as well as more area efficient as the feature size is scaled down. Moreover, digital design also benefits from mature CAD tools that simplify the design and cross-technology porting of complex systems, leveraging on a cell-based design methodology. On the other hand, the design of analog circuits is getting increasingly difficult as the feature size scales down into the deep nanometer regime due to a variety of reasons like shrinking voltage headroom, reducing intrinsic gain of the devices, increasing noise coupling between circuit nodes due to shorter distances etc. Furthermore, analog circuits are still largely designed with a full custom design ow that makes their design and porting tedious, slow, and expensive. In this context, it is attractive to consider realizing analog/mixed-signal circuits using standard digital components. This leads to scaling-friendly mixed-signal blocks that can be designed and ported using the existing CAD framework available for digital design. The concept is already being applied to mixed-signal components like frequency synthesizers where all-digital architectures are synthesized using standard cells as basic components. This can be extended to other mixed-signal blocks like digital-to-analog and analog to- digital converters as well, where the latter is of particular interest in this thesis.

A voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) is an attractive architecture to achieve all-digital analog-to digital conversion due to favorable properties like shaping of the quantization error, inherent anti-alias filtering etc. Here a VCO operates as a signal integrator as well as a quantizer. A converter employing a ring oscillator as the VCO lends itself to an all-digital implementation.

In this dissertation, we explore the design of VCO-based ADCs synthesized using digital standard cells with the long-term goal of achieving high performance data converters built from low accuracy switch components. In a first step, an ADC is designed using vendor supplied standard cells and fabricated in a 65 nm CMOS process. The converter delivers an 8-bit ENOB over a 25 MHz bandwidth while consuming 3.3 mW of power resulting in an energy efficiency of 235 fJ/step (Walden FoM). Then we utilize standard digital CAD tools to synthesize converter designs that are fully described using a hardware description language. A polynomial-based digital post-processing scheme is proposed to correct for the VCO nonlinearity. In addition, pulse modulation schemes like delta modulation and asynchronous sigma-delta modulation are used as a signal pre-coding scheme, in an attempt to reduce the impact of VCO nonlinearity on converter performance. In order to investigate the scaling benefits of all-digital data conversion, a VCO-based converter is designed in a 28 nm CMOS process. The design delivers a 13.4-bit ENOB over a 5 MHz bandwidth achieving an energy efficiency of 4.3 fJ/step according to post-synthesis schematic simulation, indicating that such converters have the potential of achieving good performance in deeply scaled processes by exploiting scaling benefits. Furthermore, large conversion errors caused by non-ideal sampling of the oscillator phase are studied. An encoding scheme employing ones counters is proposed to code the sampled ring oscillator output into a number, which is resilient to a class of sampling induced errors modeled by temporal reordering of the transitions in the ring. The proposed encoding reduces the largest error caused by random reordering of up to six subsequent bits in the sampled signal from 31 to 2 LSBs. Finally, the impact of process, voltage, and temperature (PVT) variations on the performance while operating the converter from a subthreshold supply is investigated. PVT-adaptive solutions are suggested as a means to achieve energy-efficient operation over a wide range of PVT conditions.

Ort, förlag, år, upplaga, sidor
Linköping: Linköping University Electronic Press, 2016. s. 31
Serie
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1812
Nationell ämneskategori
Elektroteknik och elektronik Signalbehandling Datavetenskap (datalogi) Telekommunikation
Identifikatorer
urn:nbn:se:liu:diva-132789 (URN)10.3384/diss.diva-1049563 (DOI)9789176856246 (ISBN)
Disputation
2016-12-16, Transformen, B-huset, Campus Valla, Linköping, 10:15 (Engelska)
Opponent
Handledare
Tillgänglig från: 2016-11-25 Skapad: 2016-11-25 Senast uppdaterad: 2019-10-29Bibliografiskt granskad

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