Comparator is the main building block in an ADC architecture. Main purpose of the comparator is to compare a signal with a reference signal and produce an output depending on whether the input signal is greater or smaller than reference. Many architectures for comparators exist for various purposes. In this thesis, Latched comparator architecture is used for sigma delta modulator. This particular design has two main characteristics that are very important for sigma delta application. First characteristic is the cancellation of memory effect which increases the speed and reliability of the system and the second is, with this architecture, high sensitivity can be achieved.

The design and implementation of lathed comparator for sigma delta modulator is presented in this thesis work. Various non-linearities and performance parameters are discussed in detail. Practical implementation and circuit design issues are highlighted to achieve maximum sensitivity along with reasonable speed and accuracy.