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FPGA-Based Hardware-In-the-Loop Co-Simulator Platform for SystemModeler
Linköpings universitet, Institutionen för systemteknik, Datorteknik.
2016 (engelsk)Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
Abstract [en]

This thesis proposes and implements a flexible platform to perform Hardware-In-the-Loop (HIL) co-simulation using a Field-Programmable-Gate-Array (FPGA). The HIL simulations are performed with SystemModeler working as a software simulator and the FPGA as the co-simulator platform for the digital hardware design. The work presented in this thesis consists of the creation of: A communication library in the host computer, a system in the FPGA that allows implementation of different digital designs with varying architectures, and an interface between the host computer and the FPGA to transmit the data. The efficiency of the proposed system is studied with the implementation of two common digital hardware designs, a PID controller and a filter. The results of the HIL simulations of those two hardware designs are used to verify the platform and measure the timing and area performance of the proposed HIL platform.

sted, utgiver, år, opplag, sider
2016. , s. 67
Emneord [en]
FPGA, Hardware-In-the-Loop, HIL, SystemModeler, Modelica, SPI, PID, Biquad
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-133413ISRN: LiTH-ISY-EX--16/5013--SEOAI: oai:DiVA.org:liu-133413DiVA, id: diva2:1059834
Eksternt samarbeid
Wolfram MathCore
Fag / kurs
Electronics Systems
Veileder
Examiner
Tilgjengelig fra: 2016-12-28 Laget: 2016-12-23 Sist oppdatert: 2016-12-28bibliografisk kontrollert

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