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Efficient FPGA Mapping of Pipeline SDF FFT Cores
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.ORCID-id: 0000-0002-1549-482X
Not Found:Linkoping Univ, Dept Elect Engn, SE-58183 Linkoping, Sweden; Tampere University of Technology, Finland.
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska fakulteten.ORCID-id: 0000-0003-3470-3911
2017 (Engelska)Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 25, nr 9, s. 2486-2497Artikel i tidskrift (Refereegranskat) Published
Abstract [en]

In this paper, an efficient mapping of the pipeline single-path delay feedback (SDF) fast Fourier transform (FFT) architecture to field-programmable gate arrays (FPGAs) is proposed. By considering the architectural features of the target FPGA, significantly better implementation results are obtained. This is illustrated by mapping an R22SDF 1024-point FFT core toward both Xilinx Virtex-4 and Virtex-6 devices. The optimized FPGA mapping is explored in detail. Algorithmic transformations that allow a better mapping are proposed, resulting in implementation achievements that by far outperforms earlier published work. For Virtex-4, the results show a 350% increase in throughput per slice and 25% reduction in block RAM (BRAM) use, with the same amount of DSP48 resources, compared with the best earlier published result. The resulting Virtex-6 design sees even larger increases in throughput per slice compared with Xilinx FFT IP core, using half as many DSP48E1 blocks and less BRAM resources. The results clearly show that the FPGA mapping is crucial, not only the architecture and algorithm choices.

Ort, förlag, år, upplaga, sidor
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC , 2017. Vol. 25, nr 9, s. 2486-2497
Nyckelord [en]
Algorithmic transformations; fast Fourier transform (FFT); field-programmable gate arrays (FPGAs); hardware mapping; single-path delay feedback (SDF)
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Datorteknik
Identifikatorer
URN: urn:nbn:se:liu:diva-140786DOI: 10.1109/TVLSI.2017.2710479ISI: 000408425400010OAI: oai:DiVA.org:liu-140786DiVA, id: diva2:1140992
Anmärkning

Funding Agencies|CENIIT at Linkoping University

Tillgänglig från: 2017-09-13 Skapad: 2017-09-13 Senast uppdaterad: 2018-01-13

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Ingemarsson, CarlKällström, PetterGustafsson, Oscar
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