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4H-SiC epitaxy investigating carrier lifetime and substrate off-axis dependence
Linköping University, Department of Physics, Chemistry and Biology, Semiconductor Materials. Linköping University, Faculty of Science & Engineering. (Semiconductor Materials)ORCID iD: 0000-0002-4235-753X
2018 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Silicon carbide (SiC) is a wide bandgap semiconductor with unique material properties making it useful for various device applications using high power, high frequency and high temperature. Compared to Si-based electronics, SiC based electronics have an improved energy efficiency. One of the most critical problems is to reduce this planets power consumption, where large improvements can be made enhancing the energy efficiency. Independent on how the electrical power is generated, power conversion is needed and about 10% of the electrical power is lost for every power conversion step using Si-based electronics. Since the efficiency is related to the performance of the semiconductor device, SiC can make contributions to the efficiency. Compared to Si, SiC has three times larger bandgap, about ten times higher breakdown electric field strength and about three times higher thermal conductivity. The wide bandgap together with the chemical stability of SiC makes it possible for SiC electronic devices to operate at much higher temperatures (>250°C) compared to Si-based devices and do not require large cooling units as with Si power converters.

The current status for 4H-SiC devices regard unipolar devices (≤ 1700 V), such as metal-oxide-semiconductor field-effect transistors (MOSFETs) and Schottky barrier diodes (SBDs), are now on the market for mass production. The research focus is now on high-voltage (>10 kV) bipolar devices, such as, bipolar junction transistors (BJTs), p‑i‑n diodes and insulated-gate bipolar transistors (IGBTs).

The focus of this thesis are material improvements relevant for the development of 4H-SiC high-voltage bipolar devices. A key parameter for such devices is the minority carrier lifetime, where long carrier lifetimes reduce the on-resistance through conductivity modulation. However, too long carrier lifetimes give long reverse recovery times leading to large switching losses. Thus, a tailored carrier lifetime is needed for the specific application. Carrier lifetimes of the epilayers can both be controlled by the CVD growth conditions and by post-growth processing, such as thermal oxidation and carbon implantation followed by thermal annealing. Emphasis in this thesis (Paper 1‑2) is to find optimal CVD growth conditions (growth temperature, C/Si ratio, growth rate, doping) improving the carrier lifetime. Since the main lifetime limiting defect has shown to be the Z1/2 center, identified as isolated carbon vacancies, growth conditions minimizing the Z1/2 concentration are strived for.

To achieve high-voltage bipolar devices, thick epilayers of high quality is needed. An important factor is then the growth rate that needs to be relatively high in order to reduce the fabrication time, and thus the cost of the final device. In this thesis the growth process has been optimized for high growth rates (30 µm/h) using standard silane and propane chemistry (Paper 3), compared to other chemistries that includes chlorine, which results in corroded reactor parts and new defects in the epitaxial layers.

Another important parameter for 4H-SiC bipolar devices is the basal plane dislocations (BPDs) in the substrate and epilayers, since the BPDs can act as source of nucleation and expansion of Shockley stacking faults (SSFs). The expanded SSFs give a lowered carrier lifetime and form a potential barrier for carrier transport leading to an increased forward voltage drop which in turn leads to bipolar degradation. The bipolar degradation is detrimental for 4H-SiC bipolar devices. Several strategies are developed to reduce the density of BPDs including buffer layers, growth interrupts and decreasing the substrates off-cut angle. Paper 4‑6 is focused on developing a CVD growth process for low substrate off-cut angles (1° and 2°) compared to the today’s standard off-cut angle of 4°. By reducing the substrate off-cut angle the number of BPDs intersecting the substrate surface is reduced. In addition, the conversion from BPDs to threading edge dislocations (TEDs) during epitaxial growth is increased with lower off-cut angles.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2018. , p. 63
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1960
National Category
Materials Engineering
Identifiers
URN: urn:nbn:se:liu:diva-152500DOI: 10.3384/diss.diva-152500ISBN: 9789176851937 (print)OAI: oai:DiVA.org:liu-152500DiVA, id: diva2:1260934
Public defence
2018-12-18, Planck, Fysikhuset, Campus Valla, Linköping, 10:15 (English)
Opponent
Supervisors
Available from: 2018-12-10 Created: 2018-11-05 Last updated: 2019-09-30Bibliographically approved
List of papers
1. Influence of Growth Temperature on Carrier Lifetime in 4H-SiC Epilayers
Open this publication in new window or tab >>Influence of Growth Temperature on Carrier Lifetime in 4H-SiC Epilayers
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2013 (English)Conference paper, Published paper (Refereed)
Abstract [en]

Carrier lifetime and formation of defects have been investigated as a function of growth temperature in n-type 4H-SiC epitaxial layers, grown by horizontal hot-wall CVD. Emphasis has been put on having fixed conditions except for the growth temperature, hence growth rate, doping and epilayer thickness were constant in all epilayers independent of growth temperature. An increasing growth temperature gave higher Z1/2 concentrations along with decreasing carrier lifetime. A correlation between growth temperature and D1 defect was also observed.

Place, publisher, year, edition, pages
Trans Tech Publications Inc., 2013
Keywords
Atomic Force Microscopy, Carrier Lifetime, DLTS, Epitaxial Growth, Horizontal Hot-Wall CVD, Intrinsic Defect, Photoluminescence (PL)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-88341 (URN)10.4028/www.scientific.net/MSF.740-742.637 (DOI)000319785500151 ()
Conference
9th European Conference on Silicon Carbide and Related Materials (ECSCRM 2012), 2-6 September 2012, St Petersburg, Russia
Available from: 2013-02-04 Created: 2013-02-04 Last updated: 2018-12-10
2. Smooth 4H-SiC epilayers grown with high growth rates with silane/propane chemistry using 4° off-cut substrates
Open this publication in new window or tab >>Smooth 4H-SiC epilayers grown with high growth rates with silane/propane chemistry using 4° off-cut substrates
2016 (English)In: Silicon Carbide and Related Materials 2015 / [ed] Fabrizio Roccaforte, Francesco La Via, Roberta Nipoti, Danilo Crippa, Filippo Giannazzo and Mario Saggio, Trans Tech Publications, 2016, Vol. 858, p. 209-212Conference paper, Published paper (Refereed)
Abstract [en]

4H-SiC epilayers with very smooth surfaces were grown with high growth rates on 4° off-cut substrates using standard silane/propane chemistry. Specular surfaces with RMS values below 0.2 nm are presented for epilayers grown with growth rates up to 30 μm/h using horizontal hot-wall chemical vapor deposition, with up to 100 μm thickness. Optimization of in-situ etching conditions and C/Si ratio are presented.

Place, publisher, year, edition, pages
Trans Tech Publications, 2016
Series
Materials Science Forum, ISSN 1662-9752 ; 858
Keywords
Atomic force microscopy, Chemical vapor deposition, Epitaxial growth, Silicon carbide
National Category
Materials Engineering
Identifiers
urn:nbn:se:liu:diva-153288 (URN)10.4028/www.scientific.net/MSF.858.209 (DOI)
Conference
The 16th International Conference on Silicon Carbide and Related Materials (ICSCRM2015), Giardini Naxos, Sicily, Italy, October 4th October 9th, 2015.
Available from: 2018-12-10 Created: 2018-12-10 Last updated: 2019-01-10
3. Improved Epilayer Surface Morphology on 2 degrees off-cut 4H-SiC Substrates
Open this publication in new window or tab >>Improved Epilayer Surface Morphology on 2 degrees off-cut 4H-SiC Substrates
2014 (English)In: SILICON CARBIDE AND RELATED MATERIALS 2013, PTS 1 AND 2, Trans Tech Publications , 2014, Vol. 778-780, p. 206-209Conference paper, Published paper (Refereed)
Abstract [en]

Homoepitaxial layers of 4H-SiC were grown with horizontal hot-wall CVD on 2 degrees off-cut substrates, with the purpose of improving the surface morphology of the epilayers and reducing the density of surface morphological defects. In-situ etching conditions in either pure hydrogen or in a mixture of silane and hydrogen prior to the growth were compared as well as C/Si ratios in the range 0.8 to 1.0 during growth. The smoothest epilayer surface, together with lowest defect density, was achieved with growth at a C/Si ratio of 0.9 after an in-situ etching in pure hydrogen atmosphere.

Place, publisher, year, edition, pages
Trans Tech Publications, 2014
Series
Materials Science Forum, ISSN 1662-9752 ; 778-780
Keywords
epitaxial growth; horizontal hot-wall CVD; atomic force microscopy; vicinal off angle
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-108194 (URN)10.4028/www.scientific.net/MSF.778-780.206 (DOI)000336634100048 ()
Conference
SILICON CARBIDE AND RELATED MATERIALS 2013
Available from: 2014-06-26 Created: 2014-06-26 Last updated: 2018-12-10
4. In-grown stacking-faults in 4H-SiC epilayers grown on 2 degrees off-cut substrates
Open this publication in new window or tab >>In-grown stacking-faults in 4H-SiC epilayers grown on 2 degrees off-cut substrates
2015 (English)In: Physica status solidi. B, Basic research, ISSN 0370-1972, E-ISSN 1521-3951, Vol. 252, no 6, p. 1319-1324Article in journal (Refereed) Published
Abstract [en]

4H-SiC epilayers were grown on 2 degrees off-cut substrates using standard silane/propane chemistry, with the aim of characterizing in-grown stacking faults. The stacking faults were analyzed with low temperature photoluminescence spectroscopy, room temperature photoluminescence mappings, room temperature cathodoluminescence and synchrotron white beam X-ray topography. At least three different types of in-grown stacking faults were observed, including double Shockley stacking faults, triple Shockley stacking faults and bar-shaped stacking faults. Those stacking faults are all previously found in 4 degrees and 8 degrees off-cut epilayers; however, the geometrical size is larger in epilayers grown on 2 degrees off-cut substrates due to lower off-cut angle. The stacking faults were formed close to the epilayer/substrate interface during the epitaxial growth. (C) 2015 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim

Place, publisher, year, edition, pages
WILEY-V C H VERLAG GMBH, 2015
Keywords
chemical vapor deposition; epitaxy; photoluminescence; SiC; stacking faults
National Category
Chemical Sciences
Identifiers
urn:nbn:se:liu:diva-120065 (URN)10.1002/pssb.201451710 (DOI)000355756200018 ()
Note

Funding Agencies|Swedish Research Council (VR); Advanced Functional Materials (AFM); Swedish Foundation for Strategic Research (SSF)

Available from: 2015-07-06 Created: 2015-07-06 Last updated: 2019-10-14

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