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Area-efficient scheduling scheme based FFT processor for various OFDM systems
Dongbu Hitek, South Korea.
Ajou University, South Korea.
Ajou University, South Korea.
Linköpings universitet, Institutionen för systemteknik, Datorteknik.ORCID-id: 0000-0003-3470-3911
2018 (engelsk)Konferansepaper, Oral presentation only (Annet vitenskapelig)
Abstract [en]

This paper presents an area-efficient fast Fouriertransform (FFT) processor for orthogonal frequency-division multiplexing systems based on multi-path delay commutator architecture. This paper proposes a data scheduling scheme to reduce the number of complex constant multipliers. The proposed mixed-radix multi-path delay commutator FFT processor can support 128-, 256-, and 512-point FFT sizes. The proposed processor was synthesized using the Samsung 65-nm CMOS standard cell library. The proposed processor with eight parallel data paths can achieve a high throughput rate of up to 2.64 GSample/s at 330 MHz.

sted, utgiver, år, opplag, sider
2018.
Emneord [en]
fast Fourier transform (FFT); high throughput; low hardware complexity; mixed-radix multi-path delay commutator (MRMDC); orthogonal frequency-division multiplexing (OFDM) systems
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-153114OAI: oai:DiVA.org:liu-153114DiVA, id: diva2:1266388
Konferanse
IEEE APCCAS 2018, the 14th of the biennial Asia Pacific Conference on Circuits and Systems, Chengdu, China, Oct 26-30, 2018.
Forskningsfinansiär
The Swedish Foundation for International Cooperation in Research and Higher Education (STINT)Tilgjengelig fra: 2018-11-28 Laget: 2018-11-28 Sist oppdatert: 2018-12-17

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