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All-Digital PWM Transmitters
Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
2019 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Electronic devices with wireless connectivity are fast becoming a part of daily life. According to some estimates, in the next five years, 10 billion new devices with internet connectivity would be produced. To lower the costs and extend the battery life of electronic circuits, there is an increased interest in using lowcost, low-power CMOS circuits. By taking advantage of the higher integration capabilities of modern CMOS, the analog, digital, and radio circuits can be integrated on a single die, typically called a radio-frequency system-on-chip (RF-SoC).

In an RF-SoC, most of the power is usually consumed by the radio circuits, especially the power amplifier (PA). Hence, to take advantage of the improved switching capability of transistors in modern CMOS, the use of switch-mode PAs (SMPAs) is becoming more popular. SMPAs exhibit a much higher efficiency as compared to their linear counterparts and can be easily integrated with the digital baseband circuits.

To satisfy the demand for higher data throughput, modern wireless standards like LTE and IEEE 802.11 generate envelope-varying signals using advanced modulation schemes like M-QAM and OFDM. Among several other techniques, pulse-width modulation (PWM) allows for the amplification of the envelopevarying signals using SMPAs.

The first part of this thesis explores techniques to improve the spectral performance of PWM-based transmitters. The proposed transmitters are fully digital, and the entire signal chain up to the PA can be implemented using the digital design flow, which is especially beneficial in sub-micron CMOS processes with low voltage headroom. A new transmitter is proposed that compensates for the aliasing distortion in polar PWM transmitters by using outphasing. The transmitter exhibits an improvement of up to 9 dB in dynamic range for a 1.4 MHz LTE uplink signal. The idea is extended to compensate for both image and aliasing distortions in all-digital implementations of polar PWM transmitters. By using a field programmable gate array (FPGA) and Class-D SMPAs, the proposed transmitter shows an improvement of up to 6.9 dBc in the adjacent channel leakage ratio (ACLR) and 10% in the error vector magnitude (EVM) for a 20 MHz LTE uplink signal. The proposed transmitter is fully programmable and can be easily adapted for multi-band and multi-standard transmission.

To enhance the phase linearity of all-digital PWM transmitters, a new transmitter architecture based on outphasing is presented. The proposed transmitter uses outphasing to improve the phase resolution and exhibits an improvement of 2.8 dBc and 3.3% in ACLR and EVM, respectively.

The difference between the polar and quadrature implementations of RFPWM based transmitters is explored. By using mathematical derivations and simulations, it is shown that the polar implementation outperforms the quadrature implementation due to the lower quantization noise. An RF-PWM based transmitter that eliminates both image and aliasing distortions is presented. The proposed transmitter has an all-digital implementation, uses a single SMPA, and eliminates the need for a power combiner resulting in a more compact design. For a 1.4 MHz LTE uplink signal, the proposed transmitter exhibits an improvement of up to 11.3 dBc in ACLR.

The second part of this work focuses on the design of all-digital area-efficient architectures of time-to-digital converters (TDCs). A TDC is essentially a stopwatch with a pico-second resolution and can be used to accurately quantify the pulse width and position of PWM signals.

A Vernier delay line-based TDC is presented that replaces the conventionally used sampling D flip-flops by a single transistor. This resulting implementation does not suffer from blackout time associated with D flip-flops allowing for a more compact design. The proposed TDC achieves a time resolution of 5.7 ps, and consumes 1.85 mW of power while operating at 50 MS/s.

A modified switching scheme to reduce the power consumed by the thermometerto- binary encoder used in the TDCs is presented. By taking advantage of the operating nature of the TDCs, the proposed switching scheme reduces the power consumption by up to 40% for a 256-bit encoder.

Abstract [sv]

Trådlös elektronik har snabbt blivit en del av vår vardag. Enligt uppskattningar kommer tio miljarder nya enheter anslutas till internet de närmaste fem åren. För billig och strömsnål elektronik vill man gärna använda CMOS-kretsar. Genom att utnyttja den höga integrationsförmågan med CMOS kan digitala, analoga och radiokretsar läggas samman på ett enda chip, kallat ett RF-SoC (Radio Frequency System-on-Chip).

Den största energiförbrukningen i ett RF-SoC är oftast i radiokretsarna, speciellt i sändarförstärkaren. Genom att utnyttja de allt snabbare CMOStransistorerna kan switchade förstärkare användas. Dessa har mycket mindre energiförluster jämfört med sina linjära motsvarigheter och kan enkelt integreras med digitala elektronik i en CMOS-krets.

För att tillgodose efterfrågan på högre dataöverföring används i modern trådlös datakommunikation signaler med varierande amplitud och fas samt hög bandbredd. Om vi skall kunna använda switchade förstärkare med sådana signaler, måste sändarnas arkitektur anpassas. Pulsbreddsmodulering (PWM) är en teknik som möjliggör detta.

Den första delen av denna avhandling undersöker tekniker för att förbättra spektralprestandan hos PWM-baserade sändare. De föreslagna sändarna kan konstrueras med helt digitala kretsblock fram till sändarförstärkaren.

En ny sändararkitektur som kompenserar för spegelförvrängning i polära PWM-sändare genom att använda utfasning (en klassisk teknik i äldre förstärkare) har studerats. Arkitekturen har förbättras för att kompensera för olika typer av förvrängningar av signalen som ofta uppkommer i konventionella digitala polära PWM-sändare. Genom att använda en Field-Programmable Gate Array (FPGA, ’på-plats-programmerbar grindmatris’) och switchade klass Dförstärkare, har viktiga sändarparametrar i den föreslagna sändaren förbättrats. Sändaren är helt programmerbar och kan enkelt anpassas för multiband- och multistandard-sändning.

För att förbättra faslinjäriteten hos digitala PWM-sändare presenteras en ny sändararkitektur baserad på utfasning i avhandlingen.

Skillnaden mellan polära och kvadraturimplementeringar av RF-PWMbaserade sändare har undersökts. Genom matematiska härledningar och simuleringar visar det sig att den polära implementeringen är bättre än kvadraturimplementering på grund av det lägre kvantiseringsbruset. En RF-PWM-baserad sändare som eliminerar både spegelförvrängningar och vikningsdistorsion presenteras. Den föreslagna sändaren är helt digital, använder en enda switchad förstärkare och kan konstrueras utan den annars nödvändiga effektkombineraren, vilket resulterar i en mer kompakt konstruktion.

Den andra delen av detta avhandlingsarbetet är inriktat på utformningen av helt digitala yteffektiva arkitekturer av tid-till-digital-omvandlare (time-to-digital converter, TDC). En TDC är i huvudsak ett stoppur med picosekundsupplösning och kan användas för att exakt kvantifiera pulsbredd och position för PWMsignaler.

En Vernier-fördröjningsbaserad TDC presenteras som ersätter de samplade D-vippor som brukar användas i sådana kretsar med en enda transistor. Den föreslagna kretsen lider inte av dödtider som kretsar baserade på D-vippor gör, vilket möjliggör en mer kompakt design.

Ett modifierat växlingsschema för att reducera effektförbrukningen i termometertill- binär-kodare som används i TDC:er föreslås. Genom att utnyttja TDC:ns karakteristiska beteende kan strömförbrukningen minskas med upp till 40% för en 256-bitars kodare.  

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2019. , p. 72
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1972
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-153729DOI: 10.3384/diss.diva-153729ISBN: 9789176851531 (print)OAI: oai:DiVA.org:liu-153729DiVA, id: diva2:1275760
Public defence
2019-01-31, John von Neumann, B-huset, Campus Valla, Linköping, 13:15 (English)
Opponent
Supervisors
Note

In the printed version the series name Linköping Studies in Science and Technology Thesis is incorrect. The correct series name is Linköping Studies in Science and Technology Dissertation. The series name has been corrected in the electronic version.

In the electronic version has some missing names been added in the Acknowledgement.

Available from: 2019-01-07 Created: 2019-01-07 Last updated: 2019-01-15Bibliographically approved
List of papers
1. Aliasing-Compensated Polar PWM Transmitter
Open this publication in new window or tab >>Aliasing-Compensated Polar PWM Transmitter
2017 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 64, no 8, p. 912-916Article in journal (Refereed) Published
Abstract [en]

This paper presents a novel pulse-width modulation (PWM) transmitter architecture that compensates for aliasing distortion by combining PWM and outphasing. The proposed transmitter can use either switch-mode PAs (SMPAs) or linear PAs at peak power, ensuring maximum efficiency. The transmitter shows better linearity, improved spectral performance and increased dynamic range compared to other polar PWM transmitters as it does not suffer from AM-AM distortion of the PAs and aliasing distortion due to digital PWM. Measurement results show that the proposed architecture achieves an improvement of 8 dB and 4 dB in the dynamic range compared to the digital polar PWM transmitter (PPWMT) and the aliasing-free PWM transmitter (AF-PWMT), respectively. The proposed architecture also shows better efficiency compared to the AF-PWMT.

Place, publisher, year, edition, pages
IEEE, 2017
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-136819 (URN)10.1109/TCSII.2016.2614433 (DOI)000407087200012 ()
Available from: 2017-04-27 Created: 2017-04-27 Last updated: 2019-01-07
2. A Modified All-Digital Polar PWM Transmitter
Open this publication in new window or tab >>A Modified All-Digital Polar PWM Transmitter
2018 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 65, no 2, p. 758-768Article in journal (Refereed) Published
Abstract [en]

This paper presents an all-digital polar pulsewidth modulated (PWM) transmitter for wireless communications. The transmitter combines baseband PWM and outphasing to compensate for the amplitude error in the transmitted signal due to aliasing and image distortion. The PWM is implemented in a field programmable gate array (FPGA) core. The outphasing is implemented as pulse-position modulation using the FPGA transceivers, which drive two switch-mode power amplifiers fabricated in 130-nm standard CMOS. The transmitter has an all-digital implementation that offers the flexibility to adapt it to multi-standard and multi-band signals. As the proposed transmitter compensates for aliasing and image distortion, an improvement in the linearity and spectral performance is observed as compared with a digital-PWM transmitter. For a 20-MHz LTE uplink signal, the measurement results show an improvement of up to 6.9 dBc in the adjacent channel leakage ratio.

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2018
Keywords
Software-defined radio (SDR); CMOS; FPGA; switch-mode PA (SMPA); outphasing; polar pulse-width modulation (P-PWM); aliasing distortion; image distortion; LTE
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-145245 (URN)10.1109/TCSI.2017.2725980 (DOI)000423559000029 ()
Available from: 2018-03-07 Created: 2018-03-07 Last updated: 2019-01-07
3. An All-Digital PWM Transmitter With Enhanced Phase Resolution
Open this publication in new window or tab >>An All-Digital PWM Transmitter With Enhanced Phase Resolution
2018 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 65, no 11, p. 1634-1638Article in journal (Refereed) Published
Abstract [en]

An all-digital pulse width modulated (PWM) transmitter using outphasing is proposed. The transmitter uses PWM to encode the amplitude, and outphasing for enhanced phase control. In this way, the phase resolution of the transmitter is doubled. The proposed scheme was implemented using Stratix IV FGPA and class-D PAs fabricated in a 130 nm standard CMOS. From the measurement results, a spectral performance improvement is observed due to the enhanced phase resolution. As compared to an all-digital polar PWM transmitter, the error vector magnitude for proposed transmitter is reduced by 4.1% and the adjacent channel leakage ratio shows an improvement of 5.6 dB for a 1.4 MHz LTE up-link signal for a carrier frequency of 700 MHz at the saturated output power of 25 dBm.

Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC, 2018
Keywords
Switch-mode power amplifier; polar PWM; image distortion; aliasing distortion; FPGA
National Category
Telecommunications
Identifiers
urn:nbn:se:liu:diva-152816 (URN)10.1109/TCSII.2017.2766099 (DOI)000448935400029 ()
Available from: 2018-11-22 Created: 2018-11-22 Last updated: 2019-01-07
4. Power-efficient time-to-digital converter for all-digital frequency locked loops
Open this publication in new window or tab >>Power-efficient time-to-digital converter for all-digital frequency locked loops
2015 (English)In: 2015 EUROPEAN CONFERENCE ON CIRCUIT THEORY AND DESIGN (ECCTD), Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 300-303Conference paper, Published paper (Refereed)
Abstract [en]

An 8-bit time-to-digital converter (TDC) for all-digital frequency-locked loops ispresented. The selected architecture uses a Vernier delay line where the commonlyused D flip-flops are replaced with a single enable transistor in the delay elements.This architecture allows for an area efficient and power efficient implementation. Thetarget application for the TDC is an all-digital frequency-locked loop which is alsooverviewed in the paper. A prototype chip has been implemented in a 65 nm CMOSprocess with an active core area of 75μmˆ120μm. The time resolution is 5.7 ps with apower consumption of 1.85 mW measured at 50 MHz sampling frequency.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-112589 (URN)10.1109/ECCTD.2015.7300008 (DOI)000380498200010 ()978-1-4799-9877-7 (ISBN)
Conference
European Conference on Circuit Theory and Design (ECCTD)
Available from: 2014-12-04 Created: 2014-12-04 Last updated: 2019-01-07Bibliographically approved
5. A modified switching scheme for multiplexer based thermometer-to-binary encoders
Open this publication in new window or tab >>A modified switching scheme for multiplexer based thermometer-to-binary encoders
2014 (English)In: 32nd NORCHIP Conference, 27-28 October 2014, Tampere, Finland, IEEE , 2014, p. 1-4Conference paper, Published paper (Refereed)
Abstract [en]

A modified switching scheme for thermometer-to-binary encoders used in time-to-digital converters (TDCs) is presented. The proposed scheme enables power savings up to 40% for a 256 bit encoder by taking advantage of the operating nature of the TDCs and by preventing unnecessary switchings to pass through the encoder tree. The efficiency of the proposed scheme is verified for thermometer encoders of different word lengths. It is observed that the power savings increase with the length of the thermometer encoder.

Place, publisher, year, edition, pages
IEEE, 2014
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-113278 (URN)10.1109/NORCHIP.2014.7004733 (DOI)978-1-4799-5442-1 (ISBN)
Conference
NORCHIP 2014. The Nordic Microelectronics event, 32nd Norchip Conference 27-28 October 2014, Tampere, Finland
Available from: 2015-01-14 Created: 2015-01-14 Last updated: 2019-01-24Bibliographically approved

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Touqir Pasha, Muhammad

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