liu.seSearch for publications in DiVA
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
World’s Fastest FFT Architectures: Breaking the Barrier of 100 GS/s
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.ORCID iD: 0000-0001-5739-3544
University of Kassel, Kassel, Germany.
University of Kassel, Kassel, Germany.
2019 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 66, no 4, p. 1507-1516Article in journal (Refereed) Published
Abstract [en]

This paper presents the fastest fast Fourier transform (FFT) hardware architectures so far. The architectures are based on a fully parallel implementation of the FFT algorithm. In order to obtain the highest throughput while keeping the resource utilization low, we base our design on making use of advanced shift-and-add techniques to implement the rotators and on selecting the most suitable FFT algorithms for these architectures. Apart from high throughput and resource efficiency, we also guarantee high accuracy in the proposed architectures. For the implementation, we have developed an automatic tool that generates the architectures as a function of the FFT size, input word length and accuracy of the rotations. We provide experimental results covering various FFT sizes, FFT algorithms, and field-programmable gate array boards. These results show that it is possible to break the barrier of 100 GS/s for FFT calculation.

Place, publisher, year, edition, pages
2019. Vol. 66, no 4, p. 1507-1516
Keywords [en]
Throughput, Hardware, Adders, Pipeline processing, Delays, Discrete Fourier transforms, Tools, Fast Fourier transform (FFT), fully parallel, pipelined architecture
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-155881DOI: 10.1109/TCSI.2018.2886626ISI: 000461874000018OAI: oai:DiVA.org:liu-155881DiVA, id: diva2:1300794
Note

Funding agencies:  Swedish ELLIIT Program

Available from: 2019-03-29 Created: 2019-03-29 Last updated: 2019-06-28

Open Access in DiVA

fulltext(1196 kB)74 downloads
File information
File name FULLTEXT01.pdfFile size 1196 kBChecksum SHA-512
5952345629746af45361242a547e90c758b5c6632a162e8c1ec7c4664a23954789c7b28a325a1f2f4b4e4acc043b97b4af28984056d4663eaf40221e7546ff39
Type fulltextMimetype application/pdf

Other links

Publisher's full text

Authority records BETA

Garrido, Mario

Search in DiVA

By author/editor
Garrido, Mario
By organisation
Computer EngineeringFaculty of Science & Engineering
In the same journal
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar
Total: 74 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

doi
urn-nbn

Altmetric score

doi
urn-nbn
Total: 408 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf