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Design of Two-Tone RF Generator for On-Chip IP3/IP2 Test
Linköpings universitet, Institutionen för systemteknik. Linköpings universitet, Tekniska fakulteten. Univ Management and Technol, Pakistan.
Linköpings universitet, Institutionen för systemteknik, Kommunikationssystem. Linköpings universitet, Tekniska fakulteten.
2019 (engelsk)Inngår i: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727, Vol. 35, nr 1, s. 77-85Artikkel i tidsskrift (Fagfellevurdert) Published
Abstract [en]

In this paper a built-in-self-test (BiST) aimed at the third and second intercept point (IP3/IP2) characterization of RF receiver is discussed with a focus on a stimulus generator. The generator is designed based on a specialized phase-lock loop (PLL) architecture with two voltage controlled oscillators (VCOs) operating in GHz frequency range. The objective of PLL is to keep the VCOs frequency spacing under control. According to the test requirements the phase noise and nonlinear distortion of the two-tone generator are considered as a merit for the design of VCOs and analog adder. The PLL reference spurs, critical for the IP3 measurement, are avoided by means of a frequency doubling technique. The circuit is designed in 65nm CMOS. A highly linear analog adder with OIP3amp;gt;+15dBm and ring VCOs with phase noise amp;lt; -104 dBc/Hz at 1MHz offset are used to generate the RF stimulus of total power greater than -22dBm. In simulations a performance sufficient for IP3/IP2 test of a typical RF CMOS receiver is demonstrated.

sted, utgiver, år, opplag, sider
Springer-Verlag New York, 2019. Vol. 35, nr 1, s. 77-85
Emneord [en]
BiST; IP3; IP2 test; On-chip test; Phase noise; PLL; Receiver front-end; RF stimulus; Two-tone generator
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Identifikatorer
URN: urn:nbn:se:liu:diva-156108DOI: 10.1007/s10836-019-05780-5ISI: 000461385300006Scopus ID: 2-s2.0-85061637306OAI: oai:DiVA.org:liu-156108DiVA, id: diva2:1302128
Tilgjengelig fra: 2019-04-03 Laget: 2019-04-03 Sist oppdatert: 2019-07-01bibliografisk kontrollert

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