Acceleration of Simulation Models Through Automatic Conversion to FPGA Hardware
2020 (engelsk)Inngår i: 2020 30th International Conference on Field-Programmable Logic and Applications (FPL), IEEE , 2020, s. 359-360Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]
By running simulation models on FPGAs, their execution speed can be significantly improved, at the cost of increased development effort. This paper describes a project to develop a tool which converts simulation models written in high level languages into fast FPGA hardware. The tool currently converts code written using custom C++ data types into Verilog. A model of a hybrid electric vehicle is used as a case study, and the resulting hardware runs significantly faster than on a general purpose CPU.
sted, utgiver, år, opplag, sider
IEEE , 2020. s. 359-360
Emneord [en]
FPGA, High Level Synthesis, Dynamic Programming, Hybrid Electric Vehicles
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-171274DOI: 10.1109/FPL50879.2020.00068ISI: 000679186400056ISBN: 9781728199023 (digital)ISBN: 9781728199030 (tryckt)OAI: oai:DiVA.org:liu-171274DiVA, id: diva2:1500582
Konferanse
30th International Conference on Field-Programmable Logic and Applications (FPL), Gothenburg, Sweden, 31 Aug.-4 Sept. 2020
2020-11-122020-11-122021-08-27bibliografisk kontrollert