liu.seSearch for publications in DiVA
Endre søk
RefereraExporteraLink to record
Permanent link

Direct link
Referera
Referensformat
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Annet format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annet språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf
Simulering av miljoner grindar med Count Algoritmen
Linköpings universitet, Institutionen för datavetenskap.
2004 (Svenska)Independent thesis Basic level (professional degree)OppgaveAlternativ tittel
The Counting Algorithm for simulation of million-gate designs
Abstract [en]

A key part in the development and verification of digital systems is simulation. But hardware simulators are expensive, and software simulation is not fast enough for designs with a large number of gates. As today’s digital zesigns constantly grow in size (number of gates), and that trend shows no signs to end, faster simulators handling millions of gates are needed.

We investigate how to create a software gate-level simulator able to simulate a high number of gates fast. This involves a trade-off between memory requirement and speed. A compact netlist representation can utilize cache memories more efficient but requires more work to interpret, while high memory requirements can limit the performance to the speed of main memory.

We have selected the Counting Algorithm to implement the experimental simulator MICA. The main reasons for this choice is the compact way in which gates can be stored, but still be evaluated in a simple and standard way.

The report describes the issues and solutions encountered and evaluate the resulting simulator. MICA simulates a SPARC architecture processor called Leon. Larger netlists are achieved by simulating several instances of this processor. Simulation of 128 instances is done at a speed of 9 million gates per second using only 3.5MB memory. In MICA this design correspond to 2.5 million gates.

sted, utgiver, år, opplag, sider
Institutionen för datavetenskap , 2004. , s. 46
Emneord [en]
Datorsystem, simulation, count-algorithm, gate-level, interpretive, event-driven, hierarchical, multi-queue, computer-aided design, logic evaluation, zero-delay
Emneord [sv]
Datorsystem
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-2476ISRN: LITH-IDA/DS-EX--04/046--SEOAI: oai:DiVA.org:liu-2476DiVA, id: diva2:19808
Uppsök
samhälle/juridik
Tilgjengelig fra: 2004-12-20 Laget: 2004-12-20 Sist oppdatert: 2018-01-13

Open Access i DiVA

fulltekst(273 kB)636 nedlastinger
Filinformasjon
Fil FULLTEXT01.pdfFilstørrelse 273 kBChecksum MD5
c30711849412af270f8d61e914b7467f9f02d3ec7cbd478bc3a0c585eae93cbf0c5bf861
Type fulltextMimetype application/pdf

Av organisasjonen

Søk utenfor DiVA

GoogleGoogle Scholar
Totalt: 636 nedlastinger
Antall nedlastinger er summen av alle nedlastinger av alle fulltekster. Det kan for eksempel være tidligere versjoner som er ikke lenger tilgjengelige

urn-nbn

Altmetric

urn-nbn
Totalt: 377 treff
RefereraExporteraLink to record
Permanent link

Direct link
Referera
Referensformat
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Annet format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annet språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf