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Integrating Core Selection in the SOC Test Solution Design-Flow
Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
2004 (Engelska)Ingår i: International Test conference ITC04,2004, Charlotte, NC, USA: IEEE Computer Society Press , 2004, s. 1349-Konferensbidrag, Publicerat paper (Refereegranskat)
Abstract [en]

We propose a technique to integrate core selection in the SOC (system-on-chip) test solution design-flow. It can, in contrast to previous approaches, be used in the early design-space exploration phase (the core selection process) to evaluate the impact on the system's final test solution imposed by different design decisions, i.e. the core selection and the cores test characteristics. The proposed technique includes the interdependent problems: test scheduling, TAM (test access mechanism) design, test set selection and test resource floor-planning, and it minimizes a weighted cost function based on test time and TAM routing cost while considering test conflicts and test power limitations. An advantage with the technique is the novel three-level power model: system, power-grid, and core. We have implemented and compared the proposed technique, a fast estimation technique and a computational extensive pseudo-exhaustive method, and the results demonstrate that our technique produces high quality solutions at reasonable computational cost.

Ort, förlag, år, upplaga, sidor
Charlotte, NC, USA: IEEE Computer Society Press , 2004. s. 1349-
Nyckelord [en]
testing, system-on-chip, test access mechanism, test scheduling, power optimization
Nationell ämneskategori
Datavetenskap (datalogi)
Identifikatorer
URN: urn:nbn:se:liu:diva-23266Lokalt ID: 2690OAI: oai:DiVA.org:liu-23266DiVA, id: diva2:243580
Tillgänglig från: 2009-10-07 Skapad: 2009-10-07 Senast uppdaterad: 2018-01-13

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http://www.ida.liu.se/labs/eslab/publications/pap/db/itc04.pdf

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Larsson, Erik

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Larsson, Erik
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Tekniska högskolanESLAB - Laboratoriet för inbyggda system
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