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Scheduling and Mapping of Conditional Task Graph for the Synthesis of Low Power Embedded Systems
Dept. of Electronics and Computer Science University of Southampton.
Dept. of Electronics and Computer Science University of Southampton.
Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
2003 (engelsk)Inngår i: IEE Proceedings - Computers and digital Techniques, ISSN 1350-2387, E-ISSN 1359-7027, Vol. 150, nr 5, s. 302-312Artikkel i tidsskrift (Fagfellevurdert) Published
Abstract [en]

A dynamic voltage scaling (DVS) technique for embedded systems expressed as conditional task graphs (CTGs) is described. The idea is to identify and exploit the available worst case slack time, taking into account the conditional behaviour of CTGs. Also the effect of combining a genetic algorithm based mapping with the DVS technique is examined and it is shown that further energy reduction can be achieved. The techniques are tested on a number of CTGs including a real-life example. The results show that the DVS technique can be applied to CTGs with an energy saving of up to 24%. Furthermore, it is shown that savings of up to 51% are achieved by considering during the mapping optimisation. Finally, the impact of communications and communication link selection on the scheduling and mapping technique is investigated and results are reported.

sted, utgiver, år, opplag, sider
2003. Vol. 150, nr 5, s. 302-312
Emneord [en]
dynamic voltage scaling, DVS, embedded systems, energy reduction, genetic algorithm, conditional task graphs, mapping optimization
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-23329Lokal ID: 2759OAI: oai:DiVA.org:liu-23329DiVA, id: diva2:243643
Tilgjengelig fra: 2009-10-07 Laget: 2009-10-07 Sist oppdatert: 2018-01-13

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http://www.ida.liu.se/labs/eslab/publications/pap/db/iee03_wu.pdf

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Eles, Petru Ion

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