Fast Test Cost Calculation for Hybrid BIST in Digital SystemsVise andre og tillknytning
2001 (engelsk)Inngår i: Euromicro Symposium on Digital Systems Design,2001, Warsaw, Poland: IEEE Computer Society Press , 2001, s. 318-Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]
This paper presents a hybrid BIST solution for testing systems-on-chip which combines pseudorandom test patterns with stored precomputed deterministic test patterns. A procedure is proposed for fast calculation of the cost of hybrid BIST at different lengths of pseudorandom test to find an optimal balance between test sets, and to perform core test with minimum cost of both, time and memory, and without losing in test quality. Compared to the previous approach, based on iterative use of deterministic ATPG for evaluating the cost of stored patterns, in this paper a new, extremely fast procedure is proposed, which calculates costs on a basis of fault table manipulations. Experiments on the ISCAS benchmark circuits show that the new procedure is about two orders of magnitude faster than the previous one.
sted, utgiver, år, opplag, sider
Warsaw, Poland: IEEE Computer Society Press , 2001. s. 318-
Emneord [en]
hybrid BIST, testing systems-on-chip, pseudorandom test patterns, deterministic test patterns, ATPG
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-23374Lokal ID: 2811OAI: oai:DiVA.org:liu-23374DiVA, id: diva2:243688
2009-10-072009-10-072018-01-13