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Low Complexity Hardware Interleaver for MIMO-OFDM based Wireless LAN
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
2009 (engelsk)Inngår i: Proceedings - IEEE International Symposium on Circuits and Systems, 2009, s. 1747-1750Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

A low complexity hardware interleaver architecture is presented for MIMO-OFDM based Wireless LAN e.g. 802.11n. Novelty of the presented architecture is twofold; 1) Flexibility to choose interleaver implementation with different modulation scheme and different size for different spatial streams in a multi antenna system, 2) Complexity to compute on the fly interleaver address is reduce by using recursion and is supported by mathematical formulation. The proposed interleaver architecture is implemented on 65nm CMOS process and it consumes 0.035 mm2 area. The proposed architecture supports high speed communication with maximum throughput of 900 Mbps at a clock rate of 225 MHz.

sted, utgiver, år, opplag, sider
2009. s. 1747-1750
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-21902DOI: 10.1109/ISCAS.2009.5118113ISI: 000275929801117ISBN: 978-1-4244-3828-0 (tryckt)ISBN: 978-1-4244-3827-3 (tryckt)OAI: oai:DiVA.org:liu-21902DiVA, id: diva2:246008
Konferanse
2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009; Taipei; Taiwan
Tilgjengelig fra: 2009-10-08 Laget: 2009-10-06 Sist oppdatert: 2014-09-08

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