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Formal Verification of SystemC Designs Using a Petri-Net based Representation
Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
2006 (engelsk)Inngår i: Design Automation and Test in Europe Conference DATE 2006,2006, Munich, Germany: IEEE Computer Society Press , 2006, s. 1228-Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

This paper presents an effective approach to formally verify SystemC designs. The approach translates SystemC models into a Petri-Net based representation. The Petri-net model is then used for model checking of properties expressed in a timed temporal logic. The approach is particularly suitable for, but not restricted to, models at a high level of abstraction, such as transaction-level. The efficiency of the approach is illustrated by experiments.

sted, utgiver, år, opplag, sider
Munich, Germany: IEEE Computer Society Press , 2006. s. 1228-
Emneord [en]
formal verification, SystemC, Petri-Net representation, temporal logic, model checking, transaction-level
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-31230DOI: 10.1109/DATE.2006.244076Lokal ID: 16983ISBN: 3-9810801-1-4 (tryckt)OAI: oai:DiVA.org:liu-31230DiVA, id: diva2:252053
Konferanse
Design Automation and Test in Europe Conference DATE 2006
Tilgjengelig fra: 2009-10-09 Laget: 2009-10-09 Sist oppdatert: 2018-01-13

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Forlagets fullteksthttp://www.ida.liu.se/labs/eslab/publications/pap/db/danka_date06.camera.pdf

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