liu.seSearch for publications in DiVA
Endre søk
RefereraExporteraLink to record
Permanent link

Direct link
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Annet format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annet språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf
VLSI Implementation of CRC-32 for 10 Gigabit Ethernet
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
Vise andre og tillknytning
2001 (engelsk)Inngår i: The 8th IEEE International Conference on Electronics, Circuits and Systems, 2001: ICECS 2001, 2001, s. 1215-1218Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

For 10 Gigabit Ethernet a CRC-32 generation is essential and timing critical. Many efficient software algorithms have been proposed for CRC generation. In this work we use an algorithm based on the properties of Galois fields, which gives very efficient hardware. The CRC generator has been implemented and simulated in both standard cells and a full-custom design technique. In standard cells from the UMC 0.18 micron library a throughput of 8.7 Gb/s has been achieved. In the full-custom design for AMS 0.35 micron process we have achieved a throughput of 5.0 Gb/s. The conclusion, based on extrapolation of device characteristics, is that CRC-32 generation for 10 Gb/s can be designed with standard cells in a 0.15 micron process technology, or using full-custom design techniques in a 0.18 micron process technology

sted, utgiver, år, opplag, sider
2001. s. 1215-1218
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-33606DOI: 10.1109/ICECS.2001.957433Lokal ID: 19640OAI: oai:DiVA.org:liu-33606DiVA, id: diva2:254429
Konferanse
The 8th IEEE Internationa Conference on Electronics, Circuits and Systems, Malta, September 2-5, 2001
Tilgjengelig fra: 2009-10-09 Laget: 2009-10-09 Sist oppdatert: 2013-11-07
Inngår i avhandling
1. Hardware Architecture for Protocol Processing
Åpne denne publikasjonen i ny fane eller vindu >>Hardware Architecture for Protocol Processing
2001 (engelsk)Licentiatavhandling, med artikler (Annet vitenskapelig)
Abstract [en]

Protocol processing is increasingly important. Through the years the hardware architectures for network equipment have evolved constantly. It is important to make a difference between terminals and routers and the different processing tasks they encounter. It is also important to analyze in detail the functional coverage of a hardware architecture. The maximal supported line speed is also interesting and especially which functionality can be kept at this line speed.

There are some types of hardware architectures that have gained much anention in research and from industry. Among these application specific instruction set computers, RISC with optimized instruction sets and reconfigurable hardware architectures are most often used. Very many network processors have been presented that aim for routers. So far not many protocol processors for terminals have been suggested. In terminals the requirements are different, for example low power consumption is very important for battery powered terminals.

I and my colleagues have proposed a novel way to build a protocol processor for a terminal. The main concept is to use an array of reconfigurable functional pages, which are connected in a deep pipeline. This deep pipeline serial processor is supported by a micro controller for exception handling and configuration tasks. The most performance-critical functional page in an Ethemet TCP/lP environment is the cyclic redundancy check. We allocated and scheduled the cyclic redundancy check in parallel with other functions. After having investigated different solutions we found that our functional page for cyclic redundancy check can manage 10 Gb/s, if a 0.15 micron manufacturing process is used in combination with optimized RTL code and synthesis.

Our architecture allows extensive parallel operation. The functionality is partitioned into the autonomous functional pages, which work in parallel. This reduces control overhead and simplifies the verification process. Low control overhead and extensively parallel computations admit low-power operation. The designed processor handles reception processing on a single packet or frame. It works in parallel with the host processor and significantly reduces the workload on the host processor. The designed processor always operates at line speed and supports up to 10 Gb/s.

sted, utgiver, år, opplag, sider
Linköping: Uniserv, 2001. s. 38
Serie
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 911
HSV kategori
Identifikatorer
urn:nbn:se:liu:diva-33604 (URN)19638 (Lokal ID)91-7373-209-5 (ISBN)19638 (Arkivnummer)19638 (OAI)
Presentation
2001-12-14, Sal Algoritmen, Linköpings universitet, Linköping, 13:15 (svensk)
Opponent
Tilgjengelig fra: 2009-10-09 Laget: 2009-10-09 Sist oppdatert: 2013-11-07

Open Access i DiVA

Fulltekst mangler i DiVA

Andre lenker

Forlagets fulltekst

Personposter BETA

Henriksson, TomasEriksson, HenrikNordqvist, UlfLiu, Dake

Søk i DiVA

Av forfatter/redaktør
Henriksson, TomasEriksson, HenrikNordqvist, UlfLiu, Dake
Av organisasjonen

Søk utenfor DiVA

GoogleGoogle Scholar

doi
urn-nbn

Altmetric

doi
urn-nbn
Totalt: 347 treff
RefereraExporteraLink to record
Permanent link

Direct link
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Annet format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annet språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf