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Combined Test Data Compression and Abort-on-Fail Test
Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
2006 (engelsk)Inngår i: 24th IEEE Norchip Conference,2006, Linköping: IEEE Computer Society Press , 2006Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

The increasing test data volume needed for the testing of System-on-Chips (SOCs) leads to high Automatic Test Equipment (ATE) memory requirement and long test application times. Scheduling techniques where testing can be terminated as soon as a fault appears (abort-on-fail) as well as efficient compression schemes to reduce the ATE memory requirement have been proposed separately. Previous test data compression architectures often make use of Multiple Input Signature Response Analyzers (MISRs) for response compression. Therefore, abort-on-fail testing and diagnostic capabilities are limited. In this paper, we propose an SOC test architecture that (1) allows test data compression, (2) where clock cycle based as well as patternbased abort-on-fail testing are allowed and (3) diagnostic capabilities are not reduced. We have performed experiments on ISCAS designs.

sted, utgiver, år, opplag, sider
Linköping: IEEE Computer Society Press , 2006.
Emneord [en]
testing, test data, compression, abort-on-fail
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-35465Lokal ID: 26927OAI: oai:DiVA.org:liu-35465DiVA, id: diva2:256313
Tilgjengelig fra: 2009-10-10 Laget: 2009-10-10 Sist oppdatert: 2018-01-13

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http://www.ida.liu.se/labs/eslab/publications/pap/db/erila_norchip06.pdf

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