liu.seSearch for publications in DiVA
Endre søk
RefereraExporteraLink to record
Permanent link

Direct link
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Annet format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annet språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf
Test Data Truncation for Test Quality Maximization under ATE Memory Depth Constraint
Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
2007 (engelsk)Inngår i: IET Computers and digital techniques, ISSN 1751-8601, Vol. 1, nr 1, s. 27-37Artikkel i tidsskrift (Fagfellevurdert) Published
Abstract [en]

Testing is used to ensure production of high quality integrated circuits. High test quality implies the application of high quality test data; however, technology development has led to a need to increase test data volumes to ensure high test quality. The problem is that the high test data volume leads to long test application times and high automatic test equipment memory requirement. For a modular core-based system-on-chip, a test data truncation scheme is proposed, that selects test data for each module in such a way that the system test quality is maximised while the selected test data are guaranteed to overcome constraints on time and memory. For test data selection, a test quality metric is defined based on fault coverage, defect probability and number of applied test vectors, and a scheme that selects the appropriate number of test vectors for each core, based on the test quality metric, defines the test architecture and schedules the transportation of the selected test data volume on the test access mechanism such that the system's test quality is maximised. The proposed technique has been implemented, and the experimental results, produced at reasonable CPU times on several ITC'02 benchmarks, show that high test quality can be achieved by careful selection of test data. The results indicate that the test data volume and test application time can be reduced to about 50% while keeping a high test quality.

sted, utgiver, år, opplag, sider
2007. Vol. 1, nr 1, s. 27-37
Emneord [en]
testing, electronic systems, memory constraints
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-35466Lokal ID: 26928OAI: oai:DiVA.org:liu-35466DiVA, id: diva2:256314
Tilgjengelig fra: 2009-10-10 Laget: 2009-10-10 Sist oppdatert: 2018-01-13

Open Access i DiVA

Fulltekst mangler i DiVA

Andre lenker

http://www.ida.liu.se/labs/eslab/publications/pap/db/erila_iet07.pdf

Personposter BETA

Larsson, ErikEdbom, Stina

Søk i DiVA

Av forfatter/redaktør
Larsson, ErikEdbom, Stina
Av organisasjonen

Søk utenfor DiVA

GoogleGoogle Scholar

urn-nbn

Altmetric

urn-nbn
Totalt: 41 treff
RefereraExporteraLink to record
Permanent link

Direct link
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Annet format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annet språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf