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Off-line Testing of Delay Faults in NoC Interconnects
Jönköping University, Sweden.
Tallinn University of Technology, Estonia.
Jönköping University, Sweden.
Tallinn University of Technology, Estonia.
Vise andre og tillknytning
2006 (engelsk)Inngår i: 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, 2006, IEEE Computer Society, 2006, s. 677-680Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

Testing of high density SoCs operating at high clock speeds in an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when the chip works at normal operating speed. In this paper, we propose a methodology for at-speed testing of delay faults in links connecting two distinct clock domains in a SoC. We give an analytical analysis about the efficiency of this method. We also propose a simple digital hardware structure for the receiver end of the link under test to detect delay faults. It is possible to extend our method to combine it with functional testing of the link and adapt it for on-line testing.

sted, utgiver, år, opplag, sider
IEEE Computer Society, 2006. s. 677-680
Emneord [en]
networks-on-chip, testing, delay faults
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-35468DOI: 10.1109/DSD.2006.72ISI: 000242376400091Lokal ID: 26945ISBN: 0-7695-2609-8 (tryckt)OAI: oai:DiVA.org:liu-35468DiVA, id: diva2:256316
Konferanse
9th EUROMICRO Conference on Digital System Design - Architectures, Methods and Tools (DSD 2006), 30 August-1 September 2006, Dubrovnik, Crotia
Tilgjengelig fra: 2009-10-10 Laget: 2009-10-10 Sist oppdatert: 2018-01-13

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Totalt: 199 treff
RefereraExporteraLink to record
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  • de-DE
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  • en-US
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  • nn-NB
  • sv-SE
  • Annet språk
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