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SOC Test Optimization with Compression-Technique Selection
Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
Masters Programme in Computer Science Linköpings Universitet.
Linköpings universitet, Tekniska högskolan. Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system.
Dept. of Electrical and Computer Engineering Duke University, USA.
2008 (engelsk)Inngår i: Proceedings - International Test Conference, IEEE , 2008, s. 1-Konferansepaper, Publicerat paper (Annet vitenskapelig)
Abstract [en]

The increasing test-data volumes needed for the testing of system-on-chip (SOC) lead to long test times and high memory requirements. We present an analysis to highlight the fact that the impact of a test-data compression technique on test time and compression ratio are method-dependant as well as TAM-width dependant. Therefore, we propose a technique where compression-technique selection is integrated with core wrapper design, test architecture design, and test scheduling to minimize the SOC test time and the test-data volume.

sted, utgiver, år, opplag, sider
IEEE , 2008. s. 1-
Emneord [en]
systems-on-chip, testing, compression
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-43982DOI: 10.1109/TEST.2008.4700685Lokal ID: 75304ISBN: 978-1-4244-2403-0 (tryckt)ISBN: 978-1-4244-2402-3 (tryckt)OAI: oai:DiVA.org:liu-43982DiVA, id: diva2:264843
Konferanse
A Workshop in Conjunction with the International Test Conference,2008
Tilgjengelig fra: 2009-10-10 Laget: 2009-10-10 Sist oppdatert: 2018-01-12

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