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A hardware efficient control of memory addressing for high-performance FFT processors
Royal Institute of Technoloby, Department Elect, Stockholm, Sweden.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
2000 (English)In: IEEE Transactions on Signal Processing, ISSN 1053-587X, E-ISSN 1941-0476, Vol. 48, no 3, p. 917-921p. 917-921Article in journal (Other academic) Published
Abstract [en]

The conventional memory organization of fast Fourier transform (FFT) processors is based on Cohen's scheme, Compared Kith this scheme, our scheme reduces the hardware complexity of address generation by about 50% while improving the memory access speed, Much power consumption in memory is saved since only half of the memory is activated during memory access, and the number of coefficient access is reduced to a minimum by using a nem ordering of FFT butterflies. Therefore, the new scheme is a superior solution to constructing high-performance FFT processors.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2000. Vol. 48, no 3, p. 917-921p. 917-921
Keywords [en]
conflict-free memory addressing, fast Fourier trasform, FFT coefficient access, low-power FFT processors
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-49830DOI: 10.1109/78.824693OAI: oai:DiVA.org:liu-49830DiVA, id: diva2:270726
Available from: 2009-10-11 Created: 2009-10-11 Last updated: 2019-08-20Bibliographically approved

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Wanhammar, Lars

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