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An Asic Perspective on FPGA Optimizations
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.ORCID-id: 0000-0002-0111-2384
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
2009 (engelsk)Inngår i: 19th International Conference on Field Programmable Logic and Applications (FPL), 2009, s. 218-223Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

In this paper we discuss how various design components perform in both FPGAs and standard cell based ASICs. We also investigate how various common FPGA optimizations will effect the performance and area of an ASIC port. We find that most techniques that are used to optimize a design for an FPGA will not have a negative impact on the area in an ASIC. The intended audience for this paper are engineers charged with creating designs or IP cores that are optimized for both FPGAs and ASICs.

sted, utgiver, år, opplag, sider
2009. s. 218-223
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Identifikatorer
URN: urn:nbn:se:liu:diva-50674DOI: 10.1109/FPL.2009.5272311ISI: 000277506300033ISBN: 978-1-4244-3892-1 (tryckt)ISBN: 978-1-4244-3892-1 (tryckt)OAI: oai:DiVA.org:liu-50674DiVA, id: diva2:271881
Konferanse
FPL 09: 19th International Conference on Field Programmable Logic and Applications; Prague; Czech Republic
Tilgjengelig fra: 2009-10-13 Laget: 2009-10-13 Sist oppdatert: 2015-02-18

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