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A CAD tool for synthesis of maximally fast lattice wave digital filters
Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
1999 (engelsk)Inngår i: Proc. National Conf. on Radio Science and Communication, RVK'99, 1999, s. 456-460Konferansepaper, Publicerat paper (Annet vitenskapelig)
Abstract [en]

A synthesis tool has been developed that implements the scheduling and the hardware mapping of maximally fast, bit-serial lattice wave digital filters. Such implementa­tions are of interest for use in high-speed applications or in low-power applications after supply voltage scaling. The tool generates a synthesizable VHDL hardware netlist from a set of coefficients describing the filter. The VHDL netlist is further mapped to an ASIC using tools from Mentor Graphics. Currently the tool is capable of synthesizing two lattice wave digital filter structures as well as optimizing the structure for cases like the birecip­rocal form of the filter.

sted, utgiver, år, opplag, sider
1999. s. 456-460
HSV kategori
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URN: urn:nbn:se:liu:diva-50917OAI: oai:DiVA.org:liu-50917DiVA, id: diva2:272322
Tilgjengelig fra: 2009-10-15 Laget: 2009-10-15 Sist oppdatert: 2009-10-17

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