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Multimode flex-interleaver core for baseband processor platform
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan. (Computer Engineering)
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan. (Computer Engineering)
2010 (engelsk)Inngår i: Journal of Computer Systems, Networks and Communications, ISSN 1687-7381, Vol. 2010, s. 1-16Artikkel i tidsskrift (Fagfellevurdert) Published
Abstract [en]

This paper presents a flexible interleaver architecture supportingmultiple standards likeWLAN,WiMAX, HSPA+, 3GPP-LTE, and DVB. Algorithmic level optimizations like 2D transformation and realization of recursive computation are applied, which appear to be the key to reach to an efficient hardware multiplexing among different interleaver implementations. The presented hardware enables the mapping of vital types of interleavers including multiple block interleavers and convolutional interleaver onto a single architecture. By exploiting the hardware reuse methodology the silicon cost is reduced, and it consumes 0.126mm2 area in total in 65nm CMOS process for a fully reconfigurable architecture. It can operate at a frequency of 166 MHz, providing a maximum throughput up to 664 Mbps for a multistream system and 166 Mbps for single stream communication systems, respectively. One of the vital requirements for multimode operation is the fast switching between different standards, which is supported by this hardware with minimal cycle cost overheads. Maximum flexibility and fast switchability among multiple standards during run time makes the proposed architecture a right choice for the radio baseband processing platform.

sted, utgiver, år, opplag, sider
Hindawi , 2010. Vol. 2010, s. 1-16
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-55304DOI: 10.1155/2010/793807OAI: oai:DiVA.org:liu-55304DiVA, id: diva2:315973
Tilgjengelig fra: 2010-04-29 Laget: 2010-04-29 Sist oppdatert: 2014-12-03

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