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Towards Radix-4, Parallel Interleaver Design to Support High-Throughput Turbo Decoding for Re-Configurability
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan. (Computer Engineering)
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan. (Computer Engineering)
2010 (engelsk)Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

Parallel, radix-4 turbo decoding is used to enhance the throughput and at the same time reduce the overall memory cost. The bottleneck is the higher complexity associated with radix-4 parallel interleaver implementation. This paper addresses the implementation issues of radix-4, parallel interleaver and also proposes necessary modifications in the interleaver algorithms for parallel address generation. It presents a re-configurable architecture which enables the use of same turbo decoding core to be used for multiple standards. The proposed interleaver architecture is capable of handling the memory conflicts on-the-fly. It consumes 12.5K gates and can run at a frequency of 285MHz, thus supporting a throughput of 173.3Mpbs, which can cover most of the emerging communication standards.

sted, utgiver, år, opplag, sider
IEEE , 2010. s. 1-5
Emneord [en]
Radix-4 interleaver, Parallel turbo decoding, HSPA, DVB, WiMAX, LTE
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-55305DOI: 10.1109/SARNOF.2010.5469723ISBN: 978-1-4244-5592-8 (tryckt)OAI: oai:DiVA.org:liu-55305DiVA, id: diva2:315974
Konferanse
33rd IEEE SARNOFF Symposium, Princeton, NJ, USA
Tilgjengelig fra: 2010-04-29 Laget: 2010-04-29 Sist oppdatert: 2014-10-01

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RefereraExporteraLink to record
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  • harvard1
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  • de-DE
  • en-GB
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  • sv-SE
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