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Dual standard re-configurable hardware interleaver for turbo decoding
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan. (Computer Engineering)
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan. (Computer Engineering)
2008 (engelsk)Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

A very low cost re-configurable hardwareinterleaver for two standards, 3GPP-WCMDA and 3GPPLong Term Evolution (3GPP-LTE) is presented. Theinterleaver is a key component of radio communicationsystems. Using conventional design methods, it consumes alarge part of silicon area in the design of turbo encoder anddecoder. The presented hardware interleaver addressgeneration architecture, utilizes the algorithmic levelhardware simplifications to achieve very low cost solution.After doing the hardware optimizations the proposedarchitecture consumes only 3.1k gates with a 256x8 bitmemory for the fully re-configurable dual standardinterleaver address generator. The interleaved address iscomputed every clock cycle except the case of pruning (ifblock size is less than the row-column matrix) in 3GPPWCDMA.In this case one additional clock cycle is consumedfor valid address generation.

sted, utgiver, år, opplag, sider
IEEE , 2008. s. 768-772
Emneord [en]
Hardware interleaver, WCDMA, LTE, turbo codes, permutation polynomial
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-56216DOI: 10.1109/ISWPC.2008.4556314ISBN: 978-1-4244-1652-3 (tryckt)OAI: oai:DiVA.org:liu-56216DiVA, id: diva2:317036
Konferanse
3rd International Symposium on Wireless Pervasive Computing, 2008. ISWPC'08
Tilgjengelig fra: 2010-05-01 Laget: 2010-05-01 Sist oppdatert: 2010-05-03

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