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Energy-Efficient Redundant Execution for Chip Multiprocessors
Indian Institute of Science.
Indian Institute of Science.
University of Wisconsin.
Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Tekniska högskolan.
2010 (engelsk)Inngår i: Great Lakes Symposium on VLSI on (GLSVLSI'10), Rhode Island, USA, May 16-18, 2010., New York, USA: ACM , 2010, s. 143-146Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper, we describe a power-efficient architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS) algorithm significantly reduces the energy overhead of redundant execution without sacrificing performance. Our evaluation shows that this architecture has a performance overhead of only 0.3% and consumes only 1.48 times the energy of a non-fault-tolerant baseline.

sted, utgiver, år, opplag, sider
New York, USA: ACM , 2010. s. 143-146
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Identifikatorer
URN: urn:nbn:se:liu:diva-59606DOI: 10.1145/1785481.1785516ISBN: 978-1-4503-0012-4 (tryckt)OAI: oai:DiVA.org:liu-59606DiVA, id: diva2:352630
Konferanse
20th Great Lakes Symposium on VLSI, GLSVLSI 2010; Providence, RI; United States
Tilgjengelig fra: 2010-09-29 Laget: 2010-09-21 Sist oppdatert: 2014-10-01bibliografisk kontrollert

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