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Using Partial Reconfigurability to aid Debugging of FPGA Designs
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.ORCID-id: 0000-0002-0111-2384
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
2011 (engelsk)Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

This paper discusses the use of partial reconfigurability in Xilinx FPGA designs in order to aid debugging. A debugging framework is proposed where the use of partial reconfigurability can allow for added flexibility by allowing a debugger to decide at run time what debugging module to use. This paper also presents an open source debugging tool which allows a user to read-out the contents of memory blocks in Xilinx designs without needing to use any JTAG adapter. This allows a user to debug an FPGA in situations which would otherwise be difficult, i.e. in the field.

sted, utgiver, år, opplag, sider
2011. s. 215-220
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-72273DOI: 10.1109/SPL.2011.5782651OAI: oai:DiVA.org:liu-72273DiVA, id: diva2:458860
Konferanse
VII Southern Conference on Programmable Logic (SPL)
Tilgjengelig fra: 2011-11-24 Laget: 2011-11-24 Sist oppdatert: 2015-02-18

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