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Optimizing Xilinx designs through primitive instantiation
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.ORCID-id: 0000-0002-0111-2384
2010 (engelsk)Inngår i: FPGAworld '10 Proceedings of the 7th FPGAworld Conference, New York: ACM , 2010, s. 20-27Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

This paper is intended as a guideline for people who are interested in manual instantiation of FPGA primitives as a way of improving the performance of an FPGA design. The focus of the paper is on designs where slice primitives like flip-fops and lookup tables are instantiated. Guidelines on how to develop a design with manual instantiation are presented together with a case study of a high performance bitserial two's complement divider where a majority of the area is manually instantiated. This divider is capable of reaching a maximum frequency of 345 MHz in the fastest Virtex-4 while utilizing less than 150 LUTs thanks to the high amount of manual optimizations. An open source library containing modules intended to promote the structured development of modules with manually instantiated components is also presented.

sted, utgiver, år, opplag, sider
New York: ACM , 2010. s. 20-27
Emneord [en]
FPGA, Primitive instantiation. Bit-serial divider, carry-chain
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Identifikatorer
URN: urn:nbn:se:liu:diva-72274DOI: 10.1145/1975482.1975484ISBN: 978-1-4503-0481-8 (tryckt)OAI: oai:DiVA.org:liu-72274DiVA, id: diva2:458882
Konferanse
7th FPGAworld Conference
Tilgjengelig fra: 2011-11-24 Laget: 2011-11-24 Sist oppdatert: 2015-02-18

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