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Dynamic Partial Reconfigurable FPGA
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
2011 (engelsk)Independent thesis Advanced level (degree of Master (Two Years)), 20 poäng / 30 hpOppgave
Abstract [en]

Partial Reconfigurable FPGA provides ability of reconfigure the FPGA duringrun-time. But the reconfigurable part is disabled while performing reconfiguration. In order to maintain the functionality of system, data stream should be hold for RP during that time. Due to this feature, the reconfiguration time becomes critical to designed system. Therefore this thesis aims to build a functional partial reconfigurable system and figure out how much time the reconfiguration takes.

A XILINX ML605 evaluation board is used for implementing the system, which has one static part and two partial reconfigurable modules, ICMP and HTTP. A Web Client sends different packets to the system requesting different services. These packets’ type information are analyzed and the requests are held by a MicroBlaze core, which also triggers the system’s self-reconfiguration. The reconfiguration swaps the system between ICMP and HTTP modules to handle the requests. Therefore, the reconfiguration time is defined between detection of packet type and completion of reconfiguration. A counter is built in SP for measuring the reconfiguration time.

Verification shows that this system works correctly. Analyze of test results indicates that reconfiguration takes 231ms and consumes 9274KB of storage, which saves 93% of time and 50% of storage compared with static FPGA configuration.

sted, utgiver, år, opplag, sider
2011. , s. 81
Emneord [en]
Reconfigurable FPGA, Partial Reconfiguration, ICMP, TCP, HTTP, Reconfiguring time
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-74486ISRN: LiTH-ISY-EX--11/4457--SEOAI: oai:DiVA.org:liu-74486DiVA, id: diva2:487700
Eksternt samarbeid
Ericsson AB
Fag / kurs
Computer Engineering
Presentation
2011-12-05, 13:15 (engelsk)
Uppsök
Technology
Veileder
Examiner
Tilgjengelig fra: 2012-02-14 Laget: 2012-01-30 Sist oppdatert: 2012-02-14bibliografisk kontrollert

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Dynamic Partial Reconfigurable FPGA(3090 kB)1368 nedlastinger
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