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CRC generation for protocol processing
Linköpings universitet, Institutionen för systemteknik, Elektroniska komponenter. Linköpings universitet, Tekniska högskolan.
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.
2000 (engelsk)Inngår i: Proceedings of NORCHIP 2000, 2000, s. 288-293Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

In order to provide error detection in communication networks a method called Cyclic Redundancy Check has been used for almost 40 years. This algorithm is widely used in computer networks of today and will continue to be so in the future. The implementation methods has on the other hand been constantly changing.

A comparative study of different implementation strategies for computation of Cyclic Redundancy Checks has been done in this paper. 10 different implementation strategies was examined. A novel architecture suitable for use as an IP in an protocol processor is presented. As conclusion, different implementation techniques have been divided into application areas according to their speed, flexibility and power-consumption.

sted, utgiver, år, opplag, sider
2000. s. 288-293
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-100981OAI: oai:DiVA.org:liu-100981DiVA, id: diva2:664630
Konferanse
18th NORCHIP Conference, 6-7 November, 2000, Turku, Finland
Tilgjengelig fra: 2013-11-15 Laget: 2013-11-15 Sist oppdatert: 2014-12-19
Inngår i avhandling
1. A Programmable Network Interface Accelerator
Åpne denne publikasjonen i ny fane eller vindu >>A Programmable Network Interface Accelerator
2003 (engelsk)Licentiatavhandling, med artikler (Annet vitenskapelig)
Abstract [en]

The bandwidth and number of users in computer networks are rapidly growing today. The need for added functionality in the network nodes is also increasing. The requirements on the processing devices get harder and harder to meet using traditional hardware architectures. Hence, a lot of effort is currently focused on finding new improved hardware architectures.

In the emerging research area of programmable network interfaces, there exist many hardware platform proposals. Most of them aim for router applications but not so many for terminals. This thesis explores a number of different router design alternatives and architectural concepts. The concepts have been examined to see which apply also to terminal designs.

A novel terminal platform solution is proposed in this thesis. The platform is accelerated using a programmable protocol processor. The processor uses a number of different dedicated hardware blocks, that operates in parallel, to accelerate the platform. The hardware blocks have been selected and specified to fulfill the requirements set by a number of common network protocols. To do this, the protocol processing procedure has been investigated and divided into processing tasks. The different tasks have been explored to see which are suitable for hardware acceleration and which should be processed in other parts of the platform.

The dedicated datapath, simplified control, and minimal usage of data buffers makes the proposed processor attractive from a power perspective. Further it accelerates the platform so that high speed operation is enabled.

sted, utgiver, år, opplag, sider
Linköping: Uniserv, 2003. s. 63
Serie
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 998
HSV kategori
Identifikatorer
urn:nbn:se:liu:diva-33282 (URN)19282 (Lokal ID)91-7373-580-9 (ISBN)19282 (Arkivnummer)19282 (OAI)
Tilgjengelig fra: 2009-10-09 Laget: 2009-10-09 Sist oppdatert: 2013-11-15

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