liu.seSearch for publications in DiVA
Endre søk
RefereraExporteraLink to record
Permanent link

Direct link
Referera
Referensformat
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Annet format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annet språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf
Temperature-Gradient Based Test Scheduling for 3D Stacked ICs
Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Institutionen för datavetenskap, Programvara och system. Linköpings universitet, Tekniska högskolan.
Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Institutionen för datavetenskap, Programvara och system. Linköpings universitet, Tekniska högskolan.
Linköpings universitet, Institutionen för datavetenskap, ESLAB - Laboratoriet för inbyggda system. Linköpings universitet, Institutionen för datavetenskap, Programvara och system. Linköpings universitet, Tekniska högskolan.
2013 (engelsk)Inngår i: 2013 IEEE International Conference on Electronics, Circuits, and Systems, IEEE conference proceedings, 2013, s. 405-408Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

Defects that are dependent on temperature-gradients (e.g., delay-faults) introduce a challenge for achieving an effective test process, in particular for 3D ICs. Testing for such defects must be performed when the proper temperature gradients are enforced on the IC, otherwise these defects may escape the test. In this paper, a technique that efficiently heats up the IC during test so that it complies with the specified temperature gradients is proposed. The specified temperature gradients are achieved by applying heating sequences to the cores of the IC under test trough test access mechanism; thus no external heating mechanism is required. The scheduling of the test and heating sequences is based on thermal simulations. The schedule generation is guided by functions derived from the IC's temperature equation. Experimental results demonstrate that the proposed technique offers considerable test time savings.

sted, utgiver, år, opplag, sider
IEEE conference proceedings, 2013. s. 405-408
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-106740DOI: 10.1109/ICECS.2013.6815440ISI: 000339725900110ISBN: 978-1-4799-2452-3 (tryckt)OAI: oai:DiVA.org:liu-106740DiVA, id: diva2:718368
Konferanse
20th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2013), Abu Dhabi, United Arab Emirates, December 9-12, 2013
Tilgjengelig fra: 2014-05-20 Laget: 2014-05-20 Sist oppdatert: 2018-01-11bibliografisk kontrollert

Open Access i DiVA

Fulltekst mangler i DiVA

Andre lenker

Forlagets fulltekst

Personposter BETA

Aghaee Ghaleshahi, NimaPeng, ZeboEles, Petru

Søk i DiVA

Av forfatter/redaktør
Aghaee Ghaleshahi, NimaPeng, ZeboEles, Petru
Av organisasjonen

Søk utenfor DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric

doi
isbn
urn-nbn
Totalt: 550 treff
RefereraExporteraLink to record
Permanent link

Direct link
Referera
Referensformat
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Annet format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annet språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf