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Power efficient arrangement of oversampling sigma-delta DAC
Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.ORCID-id: 0000-0002-2144-6795
2012 (engelsk)Inngår i: NORCHIP, 2012, IEEE , 2012, s. 1-4Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

A hardware efficient arrangement of digital-to-analog conversion blocks is presented by segmenting digital-to-analog converter (DAC). This segmenting of DAC is done by using buss-split design of digital sigma-delta modulator (DSDM). The reduction in the word length of input to both DSDM and DAC is analyzed with respect to performance because the input word length decides the complexity of these components. We show that effective performance can be achieved from the presented hardware efficient arrangement. All conclusions are drawn based on theory and simulations.

sted, utgiver, år, opplag, sider
IEEE , 2012. s. 1-4
Emneord [en]
digital-analogue conversion;sigma-delta modulation;DSDM;buss-split design;digital sigma-delta modulator;digital-to-analog conversion blocks;hardware efficient arrangement;oversampling sigma-delta DAC;power efficient arrangement;Complexity theory;Hardware;Modulation;Quantization;Sigma delta modulation;Signal to noise ratio;DAC complexity;Digital sigma-delta modulator;bit-split;composite architecture;modulator’s complexity;noise shaping
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-112892DOI: 10.1109/NORCHP.2012.6403119ISBN: 978-1-4673-2221-8 (tryckt)ISBN: 978-1-4673-2222-5 (tryckt)OAI: oai:DiVA.org:liu-112892DiVA, id: diva2:773513
Konferanse
2012 NORCHIP, November 12-14, Copenhagen, Denmark
Tilgjengelig fra: 2014-12-19 Laget: 2014-12-19 Sist oppdatert: 2018-11-08bibliografisk kontrollert
Inngår i avhandling
1. Complexity and Power Reduction in Digital Delta-Sigma Modulators
Åpne denne publikasjonen i ny fane eller vindu >>Complexity and Power Reduction in Digital Delta-Sigma Modulators
2014 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
Abstract [en]

A number of state-of-the-art low power consuming digital delta-sigma modulator (ΔΣ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ΔΣ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ΔΣ topologies, error-feedback modulators (EFM) are well suited for so called digital to digital modulation.

In order to meet the demands, various modifications to the conventional EFM architectures have been proposed. It is observed that if the internal and external digital signals of the EFM are not properly scaled then not only the design itself but also the signal processing blocks placed after it, may be over designed. In order to avoid the possible wastage of resources, a number of scaling criteria are derived. In this regard, the total number of signal levels of the EFM output is expressed in terms of the input scale, the order of modulation and the type of the loop filter.

Further on, it is described that the architectural properties of a unit element-based DAC allow us to move some of the digital processing of the EFM to the analog domain with no additional hardware cost. In order to exploit the architectural properties, digital circuitry of an arbitrary-ordered EFM is split into two parts: one producing the modulated output and another producing the filtered quantization noise. The part producing the modulated output is removed after representing the EFM output with a set of encoded signals. For both the conventional and the proposed EFM architectures, the DAC structure remains unchanged. Thus, savings are obtained since the bits to be converted are not accumulated in the digital domain but instead fed directly to the DAC.

A strategy to reduce the hardware of conventional EFMs has been devised recently that uses multiple cascaded EFM units. We applied the similar approach but used several cascaded modified EFM units. The compatibility issues among the units (since the output of each proposed EFM is represented by the set of encoded signals) are resolved by a number of architectural modifications. The digital processing is distributed among each unit by splitting the primary input bus. It is shown that instead of cascading the EFM units, it is enough to cascade their loop filters only. This leads not only to area reduction but also to the reduction of power consumption and critical path.

All of the designs are subjected to rigorous analysis and are described mathematically. The estimates of area and power consumption are obtained after synthesizing the designs in a 65 nm standard cell library provided by the foundry.

sted, utgiver, år, opplag, sider
Linköping: Linköping University Electronic Press, 2014. s. 70
Serie
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1640
HSV kategori
Identifikatorer
urn:nbn:se:liu:diva-112897 (URN)10.3384/diss.diva-112897 (DOI)978-91-7519-154-6 (ISBN)
Disputas
2015-01-29, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15 (engelsk)
Opponent
Veileder
Tilgjengelig fra: 2014-12-19 Laget: 2014-12-19 Sist oppdatert: 2018-11-08bibliografisk kontrollert

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