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Digital Multi-bit Cascaded Error-Feedback ΔΣ Modulators With Reduced Hardware and Power Consumption
Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.
Linköpings universitet, Institutionen för systemteknik, Elektroniksystem. Linköpings universitet, Tekniska högskolan.ORCID-id: 0000-0002-2144-6795
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.ORCID-id: 0000-0003-3470-3911
2012 (engelsk)Manuskript (preprint) (Annet vitenskapelig)
Abstract [en]

The hardware of the multi-bit digital error feedback modulator (EFM) of arbitrary order has recently been reduced by using multiple EFMs in cascade. In this paper, a modified cascading strategy is devised. Parts of the processing of consecutively placed EFM stages are merged such that a significant amount of circuitry is removed in each stage. In the proposed design, the modulated output is represented by a set of encoded signals to be used by the signal processing block placed after the EFM.

To illustrate the savings, a number of configurations of fourth-order EFM designs, composed of two- and three-cascaded stages, have been synthesized in a 65 nm CMOS process technology using conventional and the proposed implementation techniques. Savings of 52.7% and 47%, in terms of area and power consumption, respectively, at an oversampling ratio of 4 could be obtain. The trade-off between sampling frequency and hardware cost is also presented. Due to reduced hardware an increase of up to 600 MHz in the sampling frequency is achieved.

sted, utgiver, år, opplag, sider
2012. s. 1-4
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-112896OAI: oai:DiVA.org:liu-112896DiVA, id: diva2:773519
Tilgjengelig fra: 2014-12-19 Laget: 2014-12-19 Sist oppdatert: 2018-11-08bibliografisk kontrollert
Inngår i avhandling
1. Complexity and Power Reduction in Digital Delta-Sigma Modulators
Åpne denne publikasjonen i ny fane eller vindu >>Complexity and Power Reduction in Digital Delta-Sigma Modulators
2014 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
Abstract [en]

A number of state-of-the-art low power consuming digital delta-sigma modulator (ΔΣ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ΔΣ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ΔΣ topologies, error-feedback modulators (EFM) are well suited for so called digital to digital modulation.

In order to meet the demands, various modifications to the conventional EFM architectures have been proposed. It is observed that if the internal and external digital signals of the EFM are not properly scaled then not only the design itself but also the signal processing blocks placed after it, may be over designed. In order to avoid the possible wastage of resources, a number of scaling criteria are derived. In this regard, the total number of signal levels of the EFM output is expressed in terms of the input scale, the order of modulation and the type of the loop filter.

Further on, it is described that the architectural properties of a unit element-based DAC allow us to move some of the digital processing of the EFM to the analog domain with no additional hardware cost. In order to exploit the architectural properties, digital circuitry of an arbitrary-ordered EFM is split into two parts: one producing the modulated output and another producing the filtered quantization noise. The part producing the modulated output is removed after representing the EFM output with a set of encoded signals. For both the conventional and the proposed EFM architectures, the DAC structure remains unchanged. Thus, savings are obtained since the bits to be converted are not accumulated in the digital domain but instead fed directly to the DAC.

A strategy to reduce the hardware of conventional EFMs has been devised recently that uses multiple cascaded EFM units. We applied the similar approach but used several cascaded modified EFM units. The compatibility issues among the units (since the output of each proposed EFM is represented by the set of encoded signals) are resolved by a number of architectural modifications. The digital processing is distributed among each unit by splitting the primary input bus. It is shown that instead of cascading the EFM units, it is enough to cascade their loop filters only. This leads not only to area reduction but also to the reduction of power consumption and critical path.

All of the designs are subjected to rigorous analysis and are described mathematically. The estimates of area and power consumption are obtained after synthesizing the designs in a 65 nm standard cell library provided by the foundry.

sted, utgiver, år, opplag, sider
Linköping: Linköping University Electronic Press, 2014. s. 70
Serie
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1640
HSV kategori
Identifikatorer
urn:nbn:se:liu:diva-112897 (URN)10.3384/diss.diva-112897 (DOI)978-91-7519-154-6 (ISBN)
Disputas
2015-01-29, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15 (engelsk)
Opponent
Veileder
Tilgjengelig fra: 2014-12-19 Laget: 2014-12-19 Sist oppdatert: 2019-11-19bibliografisk kontrollert

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