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Area Efficient Floating-Point Adder and Multiplier with IEEE-754 Compatible Semantics
Linköpings universitet, Institutionen för systemteknik, Datorteknik. Linköpings universitet, Tekniska högskolan.ORCID-id: 0000-0002-0111-2384
2014 (engelsk)Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

In this paper we describe an open source floating-point adder andmultiplier implemented using a 36-bit custom number format based onradix-16 and optimized for the 7-series FPGAs from Xilinx. Althoughthis number format is not identical to the single-precision IEEE-754format, the floating-point operators are designed in such a way thatthe numerical results for a given operation will be identical to theresult from an IEEE-754 compliant operator with support forround-to-nearest even, NaNs and Infs, and subnormalnumbers. The drawback of this number format is that the rounding stepis more involved than in a regular, radix-2 based operator. On theother hand, the use of a high radix means that the area costassociated with normalization and denormalization can be reduced,leading to a net area advantage for the custom number format, underthe assumption that support for subnormal numbers is required.

The area of the floating-point adder in a Kintex-7 FPGA is 261 sliceLUTs and the area of the floating-point multiplier is 235 slice LUTsand 2 DSP48E blocks. The adder can operate at 319 MHz and themultiplier can operate at a frequency of 305 MHz.

sted, utgiver, år, opplag, sider
2014.
HSV kategori
Identifikatorer
URN: urn:nbn:se:liu:diva-114322OAI: oai:DiVA.org:liu-114322DiVA, id: diva2:789250
Konferanse
ICFPT2014: The 2014 International Conference on Field-Programmable Technology
Tilgjengelig fra: 2015-02-18 Laget: 2015-02-18 Sist oppdatert: 2015-02-18bibliografisk kontrollert

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hrfp_16_icfpt2014.pdf(269 kB)1611 nedlastinger
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