Design of a Gain-stage for Pipelined SAR ADC Using Capacitive Charge Pump
2016 (English)In: PROCEEDINGS OF THE 23RD INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (MIXDES 2016), IEEE , 2016, 187-190 p.Conference paper (Refereed)
This paper presents the design of a multi-stage capacitive charge pump (CCP) as a gain-stage which is used in the two-stage pipelined successive approximation analog-to-digital converter (SAR ADC). The topology of multi-stage CCP and the design considerations are provided. Thereafter, the power comparison between switch capacitor (SC) integrator and multi-stage CCP is analyzed with the parameters from 0.35-mu m CMOS process. The comparison results show that the proposed gain-stage is more power efficient than SC integrator. To verify the analysis, two types of gain-stage, SC integrator and multi-stage CCP, were simulated in 0.35-mu m CMOS process. Simulation results show that the three-stage CCP achieves a gain of 7.9 while only consuming 1.1 mu W with the gain bandwidth of 178.7 kHz. But the SC integrator consumes 1.58 times more power than CCPs to reach the similar gain and gain bandwidth.
Place, publisher, year, edition, pages
IEEE , 2016. 187-190 p.
Capacitive charge pump; successive approximation analog-to-digital converter; power consumption; pipeline; two-stage
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-132104DOI: 10.1109/MIXDES.2016.7529729ISI: 000383221700035ISBN: 978-8-3635-7808-4 (print)OAI: oai:DiVA.org:liu-132104DiVA: diva2:1038346
23rd International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES)