Multiplierless Unity-Gain SDF FFTs
2016 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 24, no 9, 3003-3007 p.Article in journal (Refereed) Published
In this brief, we propose a novel approach to implement multiplierless unity-gain single-delay feedback fast Fourier transforms (FFTs). Previous methods achieve unity-gain FFTs by using either complex multipliers or nonunity-gain rotators with additional scaling compensation. Conversely, this brief proposes unity-gain FFTs without compensation circuits, even when using nonunity-gain rotators. This is achieved by a joint design of rotators, so that the entire FFT is scaled by a power of two, which is then shifted to unity. This reduces the amount of hardware resources of the FFT architecture, while having high accuracy in the calculations. The proposed approach can be applied to any FFT size, and various designs for different FFT sizes are presented.
Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC , 2016. Vol. 24, no 9, 3003-3007 p.
Combined coefficient selection and shift-and-add implementation (CCSSI); coordinate rotation digital computer (CORDIC); fast Fourier transform (FFT); multiplierless; pipelined architecture; single-delay feedback (SDF); unity gain
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-132483DOI: 10.1109/TVLSI.2016.2542583ISI: 000384983900018OAI: oai:DiVA.org:liu-132483DiVA: diva2:1046263
Funding Agencies|Swedish ELLIIT Program2016-11-132016-11-122016-12-05