The Serial Commutator FFT
2016 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 63, no 10, 974-978 p.Article in journal (Refereed) Published
This brief presents a new type of fast Fourier transform (FFT) hardware architectures called serial commutator (SC) FFT. The SC FFT is characterized by the use of circuits for bit-dimension permutation of serial data. The proposed architectures are based on the observation that, in the radix-2 FFT algorithm, only half of the samples at each stage must be rotated. This fact, together with a proper data management, makes it possible to allocate rotations only every other clock cycle. This allows for simplifying the rotator, halving the complexity with respect to conventional serial FFT architectures. Likewise, the proposed approach halves the number of adders in the butterflies with respect to previous architectures. As a result, the proposed architectures use the minimum number of adders, rotators, and memory that are necessary for a pipelined FFT of serial data, with 100% utilization ratio.
Place, publisher, year, edition, pages
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC , 2016. Vol. 63, no 10, 974-978 p.
Fast Fourier transform (FFT); pipelined architecture; serial commutator (SC)
IdentifiersURN: urn:nbn:se:liu:diva-132529DOI: 10.1109/TCSII.2016.2538119ISI: 000385411500014OAI: oai:DiVA.org:liu-132529DiVA: diva2:1046404
Funding Agencies|Swedish ELLIIT Program2016-11-142016-11-132016-12-05