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Design of VCO-based ADCs
Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems. Linköping University, Faculty of Science & Engineering.
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Today's complex electronic systems with billions of transistors on a single die are enabled by the aggressive scaling down of the device feature size at an exponential rate as predicted by the Moore's law. Digital circuits benefit from technology scaling to become faster, more energy efficient as well as more area efficient as the feature size is scaled down. Moreover, digital design also benefits from mature CAD tools that simplify the design and cross-technology porting of complex systems, leveraging on a cell-based design methodology. On the other hand, the design of analog circuits is getting increasingly difficult as the feature size scales down into the deep nanometer regime due to a variety of reasons like shrinking voltage headroom, reducing intrinsic gain of the devices, increasing noise coupling between circuit nodes due to shorter distances etc. Furthermore, analog circuits are still largely designed with a full custom design ow that makes their design and porting tedious, slow, and expensive. In this context, it is attractive to consider realizing analog/mixed-signal circuits using standard digital components. This leads to scaling-friendly mixed-signal blocks that can be designed and ported using the existing CAD framework available for digital design. The concept is already being applied to mixed-signal components like frequency synthesizers where all-digital architectures are synthesized using standard cells as basic components. This can be extended to other mixed-signal blocks like digital-to-analog and analog to- digital converters as well, where the latter is of particular interest in this thesis.

A voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) is an attractive architecture to achieve all-digital analog-to digital conversion due to favorable properties like shaping of the quantization error, inherent anti-alias filtering etc. Here a VCO operates as a signal integrator as well as a quantizer. A converter employing a ring oscillator as the VCO lends itself to an all-digital implementation.

In this dissertation, we explore the design of VCO-based ADCs synthesized using digital standard cells with the long-term goal of achieving high performance data converters built from low accuracy switch components. In a first step, an ADC is designed using vendor supplied standard cells and fabricated in a 65 nm CMOS process. The converter delivers an 8-bit ENOB over a 25 MHz bandwidth while consuming 3.3 mW of power resulting in an energy efficiency of 235 fJ/step (Walden FoM). Then we utilize standard digital CAD tools to synthesize converter designs that are fully described using a hardware description language. A polynomial-based digital post-processing scheme is proposed to correct for the VCO nonlinearity. In addition, pulse modulation schemes like delta modulation and asynchronous sigma-delta modulation are used as a signal pre-coding scheme, in an attempt to reduce the impact of VCO nonlinearity on converter performance. In order to investigate the scaling benefits of all-digital data conversion, a VCO-based converter is designed in a 28 nm CMOS process. The design delivers a 13.4-bit ENOB over a 5 MHz bandwidth achieving an energy efficiency of 4.3 fJ/step according to post-synthesis schematic simulation, indicating that such converters have the potential of achieving good performance in deeply scaled processes by exploiting scaling benefits. Furthermore, large conversion errors caused by non-ideal sampling of the oscillator phase are studied. An encoding scheme employing ones counters is proposed to code the sampled ring oscillator output into a number, which is resilient to a class of sampling induced errors modeled by temporal reordering of the transitions in the ring. The proposed encoding reduces the largest error caused by random reordering of up to six subsequent bits in the sampled signal from 31 to 2 LSBs. Finally, the impact of process, voltage, and temperature (PVT) variations on the performance while operating the converter from a subthreshold supply is investigated. PVT-adaptive solutions are suggested as a means to achieve energy-efficient operation over a wide range of PVT conditions.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2016. , 31 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1812
National Category
Electrical Engineering, Electronic Engineering, Information Engineering Signal Processing Computer Science Telecommunications
Identifiers
URN: urn:nbn:se:liu:diva-132789DOI: 10.3384/diss.diva-1049563ISBN: 9789176856246 (print)OAI: oai:DiVA.org:liu-132789DiVA: diva2:1049563
Public defence
2016-12-16, Transformen, B-huset, Campus Valla, Linköping, 10:15 (English)
Opponent
Supervisors
Available from: 2016-11-25 Created: 2016-11-25 Last updated: 2017-05-12Bibliographically approved
List of papers
1. Time-Mode Analog-to-Digital Conversion Using Standard Cells
Open this publication in new window or tab >>Time-Mode Analog-to-Digital Conversion Using Standard Cells
2014 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 12, 3348-3357 p.Article in journal (Refereed) Published
Abstract [en]

Synthesizable all-digital ADCs that can be designed, verified and taped out using a digital design flow are of interest due to a consequent reduction in design cost and an improved technology portability. As a step towards high performance synthesizable ADCs built using generic and low accuracy components, an ADC designed exclusively with standard digital cell library components is presented. The proposed design is a time-mode circuit employing a VCO based multi-bit quantizer. The ADC has first order noise-shaping due to inherent error feedback of the oscillator and sinc anti-aliasing filtering due to continuous-time sampling. The proposed architecture employs a Gray-counter based quantizer design, which mitigates the problem of partial sampling of digital data in multi-bit VCO-based quantizers. Furthermore, digital correction employing polynomial-fit estimation is proposed to correct for VCO non-linearity. The design occupies 0.026 mm when fabricated in a 65 nm CMOS process and delivers an ENOB of 8.1 bits over a signal bandwidth of 25.6 MHz, while sampling at 205 MHz. The performance is comparable to that of recently reported custom designed single-ended open-loop VCO-based ADCs, while being designed exclusively with standard cells, and consuming relatively low average power of 3.3 mW achieving an FoM of 235 fJ/step.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2014
Keyword
ADC; all-digital; analog-to-digital; Gray-counter; linearization; polynomial-fit; standard cell; synthesizable; time-domain; time-mode; VCO-based ADC
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-113048 (URN)10.1109/TCSI.2014.2340551 (DOI)000345581200004 ()
Available from: 2015-01-09 Created: 2015-01-08 Last updated: 2016-11-25
2. A Fully Synthesized All-Digital VCO-Based Analog-to-Digital Converter
Open this publication in new window or tab >>A Fully Synthesized All-Digital VCO-Based Analog-to-Digital Converter
2015 (English)In: 2015 NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS) - NORCHIP and INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP (SOC), Institute of Electrical and Electronics Engineers (IEEE), 2015Conference paper (Refereed)
Abstract [en]

Synthesis of all-digital ADCs leads to significant reduction in design cost and design time, besides improving cross-technology portability. In this work, an ADC which is fully described in digital HDL is synthesized, placed and routed using standard digital design tools. A VCO-based architecture is chosen for its synthesizability. The design flow employed is discussed. The circuit is synthesized using the standard cell library in a 65 nm CMOS process, delivering a resolution of 9 ENOB over 10 MHz bandwidth according to post layout parasitic extracted simulations using the Spectre simulator. Post synthesis and post place-and-route performances are provided.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015
National Category
Aerospace Engineering
Identifiers
urn:nbn:se:liu:diva-131246 (URN)10.1109/NORCHIP.2015.7364386 (DOI)000380441400033 ()9781467365765 (ISBN)9781467365758 (ISBN)9781467365772 (ISBN)
Conference
Nordic Circuits Systems Conference (NORCAS): NORCHIP & International Symposium on System Chip (SoC) 2015, 26-28 October, Oslo, Norway
Available from: 2016-09-16 Created: 2016-09-12 Last updated: 2016-11-25
3. A NAND Gate Based Standard Cell VCO for Use in Synthesizable ADCs
Open this publication in new window or tab >>A NAND Gate Based Standard Cell VCO for Use in Synthesizable ADCs
2015 (English)In: 2015 NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS) - NORCHIP and INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP (SOC), IEEE , 2015Conference paper (Refereed)
Abstract [en]

Synthesizable all-digital ADCs lead to reduced design cost and design time as well as to low cross-technology porting costs. VCO-based ADC is an attractive candidate for the synthesis of ADCs using standard cells. However, a VCO, which is controlled by an analog input signal, is difficult to implement using standard digital circuits. Supply controlled ring oscillators using static CMOS inverters are used in prior works. In this work, an alternative VCO built using NAND gates is proposed for use in synthesizable converters. The circuit is demonstrated by employing it in an ADC synthesized from an HDL description. Transistor level simulation of the resulting netlist using the Spectre simulator shows that a performance of 10 bit ENOB over a 10 MHz bandwidth can be achieved after digital correction, using the proposed VCO.

Place, publisher, year, edition, pages
IEEE, 2015
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-131245 (URN)10.1109/NORCHIP.2015.7364398 (DOI)000380441400045 ()9781467365765 (ISBN)9781467365758 (ISBN)9781467365772 (ISBN)
Conference
Nordic Circuits Systems Conference (NORCAS): NORCHIP & International Symposium on System Chip (SoC) 2015,26-28 October, Oslo, Norway
Available from: 2016-09-16 Created: 2016-09-12 Last updated: 2016-11-25
4. Linearization of Synthesizable VCO-Based ADCs Using Delta Modulation
Open this publication in new window or tab >>Linearization of Synthesizable VCO-Based ADCs Using Delta Modulation
2015 (English)In: 2015 European Conference on Circuit Theory and Design (ECCTD), Institute of Electrical and Electronics Engineers (IEEE), 2015, 280-283 p.Conference paper (Refereed)
Abstract [en]

VCO-based ADC is an attractive candidate for the synthesis of all-digital ADCs using standard cells. However, the non-linearity of a synthesizable VCO requires digital post-processing to obtain good performance. We propose another solution where the input analog signal is pre-coded into a delta-modulated pulse stream which is used to drive a VCO-based converter. This causes the oscillator to operate at two distinct frequencies thereby eliminating the VCO non-linearity from the converter transfer function. A circuit is proposed that consists of a synthesized digital block realizing all the active parts of the circuit and a passive RC net used as an integrator. Spectre simulation of the netlist synthesized using a 65 nm standard cell library shows a performance of 8.2 bit ENOB over a 3 MHz bandwidth without using any digital post-processing.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-131533 (URN)10.1109/ECCTD.2015.7300003 (DOI)000380498200005 ()9781479998777 (ISBN)9781479998760 (ISBN)9781479998784 (ISBN)
Conference
European Conference on Circuit Theory and Design (ECCTD), 24-26 August, Trondheim, Norway
Available from: 2016-09-25 Created: 2016-09-23 Last updated: 2016-11-25
5. Mixed-Signal Design Using Digital CAD
Open this publication in new window or tab >>Mixed-Signal Design Using Digital CAD
2016 (English)In: Proceedings IEEE Computer Society Annual Symposium on VLSI ISVLSI 2016, 2016, 6-11 p.Conference paper (Refereed)
Abstract [en]

The paper investigates the use of the existing CAD framework for digital circuit synthesis to design and synthesize a select set of mixed-signal functions like analog-to-digital and digital-to-analog conversions. This approach leads to fast and low cost design of technology portable system-on-chip solutions with analog interfaces. Some circuit examples for implementation of data conversion using digital circuits are discussed, leveraging on time-domain signal processing. Some of the signal corruption mechanisms in time-domain signal processing systems are considered in order to suggest adaptations to the existing digital design flow for the synthesis of mixed-signal circuits. As an example to show that high performance data conversion circuits can be realized using low accuracy general purpose components, an ADC is designed and synthesized with the vendor supplied standard cell library in a 65 nm CMOS process. Spectre simulation results show the feasibility of employing a digital CAD framework to synthesize high performance mixed-signal circuits, by applying time-domain signal processing.

Series
IEEE Computer Society Annual Symposium on VLSI, ISSN 2159-3477
Keyword
CAD;analogue-digital conversion;digital-analogue conversion;electronic engineering computing;integrated circuit design;mixed analogue-digital integrated circuits;signal processing;system-on-chip;time-domain analysis;ADC design;CAD framework;CMOS process;Spectre simulation;analog interfaces;analog-to-digital conversion;corruption mechanisms;data conversion;digital CAD framework;digital circuit synthesis;digital design flow;digital-to-analog conversion;high-performance data conversion circuits;mixed-signal circuit synthesis;mixed-signal design;mixed-signal functions;size 65 nm;system-on-chip design;time-domain signal processing;time-domain signal processing systems;vendor supplied standard cell library;Delays;Digital circuits;Inverters;Logic gates;Signal processing;Standards;Time-domain analysis;ADC;CAD;DAC;Mixed-signal;VHDL;Verilog;all-digital;analog;analog-to-digital;comparator;design flow;digital;digital-to-analog;opamp;place-and-route;signal processing;synthesis;synthesizable;time-domain;time-mode
National Category
Electrical Engineering, Electronic Engineering, Information Engineering Computer Engineering
Identifiers
urn:nbn:se:liu:diva-132788 (URN)10.1109/ISVLSI.2016.79 (DOI)000389508400002 ()9781467390392 (ISBN)9781467390408 (ISBN)
Conference
IEEE Computer Society Annual Symposium on VLSI, 11-13 July 2016, Pittsburgh, Pennsylvania, USA
Available from: 2016-11-25 Created: 2016-11-25 Last updated: 2016-12-30Bibliographically approved
6. Linearization of VCO-based ADCs using asynchronous sigma-delta modulation
Open this publication in new window or tab >>Linearization of VCO-based ADCs using asynchronous sigma-delta modulation
2016 (English)Conference paper (Refereed)
Abstract [en]

Asynchronous sigma-delta modulation is investigated as an alternative linearization scheme for all-digital voltage controlled oscillator based analog-to-digital converters, which commonly require digital post processing to achieve good linearity. The modulator output, when used to drive a VCO-based converter, causes the oscillator to operate at two fixed frequencies thereby removing the VCO nonlinearity from the transfer function. A circuit is proposed consisting of a digital block and a passive RC circuit operating as an integrator. Spectre simulation of the design synthesized using a 65 nm standard cell library indicate that a harmonic suppression up to -60 dB is feasible.

Place, publisher, year, edition, pages
New York: Institute of Electrical and Electronics Engineers, 2016
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering Control Engineering Signal Processing Computational Mathematics Mathematical Analysis
Identifiers
urn:nbn:se:liu:diva-136115 (URN)10.1109/MWSCAS.2016.7870151 (DOI)
Conference
2016 IEEE 59th International Midwest Symposium on : Circuits and Systems (MWSCAS), 16-19 October, 2016
Available from: 2017-03-28 Created: 2017-03-28 Last updated: 2017-04-24Bibliographically approved
7. Design of a VCO-based ADC in 28 nm CMOS
Open this publication in new window or tab >>Design of a VCO-based ADC in 28 nm CMOS
2016 (English)In: 2016 2ND IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS), IEEE , 2016Conference paper (Refereed)
Abstract [en]

A VCO-based ADC is designed and synthesized in a 28 nm FDSOI CMOS process to investigate the scaling benefits of all-digital analog-to-digital conversion. A coarse-fine quantizer is used to obtain high energy efficiency. Common patterns of sample errors at the multi-phase VCO output are identified and mitigated. Final design indicates an ENOB of 13.4 and a Walden FoM of 4.3 fJ/step over a 5 MHz bandwidth while sampling at 150 MHz, according to schematic simulation of the synthesized netlist.

Place, publisher, year, edition, pages
IEEE, 2016
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-134514 (URN)10.1109/NORCHIP.2016.7792914 (DOI)000391620400041 ()978-1-5090-1095-0 (ISBN)
Conference
2nd IEEE Nordic Circuits and Systems Conference (NORCAS)
Available from: 2017-02-15 Created: 2017-02-15 Last updated: 2017-03-28
8. VCO-based ADCs for IoT applications
Open this publication in new window or tab >>VCO-based ADCs for IoT applications
2016 (English)In: 2016 International Symposium on Integrated Circuits (ISIC), IEEE Press, 2016, 1-4 p.Conference paper (Refereed)
Abstract [en]

Internet of things (IoT) benefits from fast and low cost development of technology portable re-configurable hardware. Low power consumption is desired for applications operating from harvested or limited energy. Subthreshold operation of VCO-based ADCs is investigated in this work in order to meet these challenges. A ring VCO built using NAND gates is used for reliable operation in the subthreshold region. The impact of supply scaling and PVT variations on the VCO characteristics as well as on the converter performance is studied using transistor level simulations. Some solutions are suggested towards energy efficient operation over a wide range of PVT conditions.

Place, publisher, year, edition, pages
IEEE Press, 2016
Series
International Symposium on Integrated Circuits, ISSN 2325-0631
Keyword
Internet of Things;NAND circuits;analogue-digital conversion;circuit reliability;low-power electronics;voltage-controlled oscillators;ADC;Internet of Things;IoT applications;NAND gates;energy efficient operation;portable reconfigurable hardware;process variations;ring VCO;temperature variations;voltage variations;Bandwidth;Libraries;Logic gates;Power demand;Registers;Voltage-controlled oscillators
National Category
Energy Systems Other Electrical Engineering, Electronic Engineering, Information Engineering Energy Engineering Other Engineering and Technologies not elsewhere specified Other Environmental Engineering
Identifiers
urn:nbn:se:liu:diva-136120 (URN)10.1109/ISICIR.2016.7829746 (DOI)000400693600073 ()
Conference
International Symposium on Integrated Circuits (ISIC),12-14 December, 2016
Note

Funding agencies: Swedens innovation agency; Swedish Research Council Formas; Swedish Energy Agency [2015-01305]; European Unions [644378]

Available from: 2017-03-28 Created: 2017-03-28 Last updated: 2017-06-13Bibliographically approved
9. Mitigation of Sampling Errors in VCO-Based ADCs
Open this publication in new window or tab >>Mitigation of Sampling Errors in VCO-Based ADCs
2017 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, no 99, 1-10 p.Article in journal (Refereed) Published
Abstract [en]

Voltage-controlled-oscillator-based analog-to-digital converter (ADC) is a scaling-friendly architecture to build ADCs in fine-feature complimentary metal-oxide-semiconductor processes. Lending itself to an implementation with digital components, such a converter enables design automation with existing digital CAD hence reducing design and porting costs compared with a custom design flow. However, robust architectures and circuit techniques that reduce the dependence of performance on component accuracy are required to achieve good performance while designing converters with low accuracy components like standard cells in deeply-scaled processes. This paper investigates errors resulting from the sampling of a fast switching multi-phase ring oscillator output. A scheme employing ones-counters is proposed to encode the sampled ring oscillator code into a binary representation, which is resilient to a class of sampling induced errors modeled by the temporal reordering of the transitions in the ring. In addition to correcting errors caused by deterministic reordering, proposed encoding suppresses conversion errors in the presence of arbitrary reordering patterns that may result from automatic place-and-route in wire-delay dominated processes. The error suppression capability of the encoding is demonstrated using MATLAB simulation. The proposed encoder reduces the error caused by the random reordering of six subsequent bits in the sampled signal from 31 to 2 LSBs for a 31-stage oscillator.

Place, publisher, year, edition, pages
New York: Institute of Electrical and Electronics Engineers (IEEE), 2017
Keyword
Analog-to-digital, VCO-based, ADC, sampling error, time-domain, synthesis, deep submicrometer technology, error correction, encoding, ring oscillator, ones-counter, non-ideal sampling, synthesis, place-and-route, sigma-delta
National Category
Signal Processing Embedded Systems Computer Engineering Telecommunications
Identifiers
urn:nbn:se:liu:diva-137327 (URN)10.1109/TCSI.2017.2670058 (DOI)
Available from: 2017-05-12 Created: 2017-05-12 Last updated: 2017-05-19Bibliographically approved

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